Scott K. Springer

Record RF performance of 45-nm SOI CMOS Technology

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fTs of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fTs are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond

SOI CMOS Technology with 360GHz f T NFET, 260GHz f T PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fTs of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging device modeling features and their enhancements. At nominal Lpoly, floating-body NFET and PFET demonstrate peak fT of 300GHz and fMAX of higher than 350GHz with excellent model-to-hardware accuracy. For precision analog circuit design, body-contacted (BC) FETs and various passives are offered, and their performance and modeling accuracy are co-optimized to push the technology limit and achieve state-of-the-art circuits, e.g., 28Gb/s serial link transceiver and LC-tank VCO operating at higher than 100GHz.

Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch

In this brief, threshold voltage mismatch of fully integrated n-type FinFETs based on a gate-first process was studied experimentally. Significantly improved threshold voltage mismatch due to undoped FIN body was confirmed with the experimental data. By comparing mismatch values of thin- and thick-oxide nMOS, we found that factors, which do not scale with gate oxide thickness, including line edge roughness and metal-gate granularity (MGG), can explain ~ 60% of total mismatch of thin-oxide devices. Moreover, we report a convex shape of threshold voltage mismatch following the increase of the number of FINs and propose a possible explanation of the abnormal behavior. Due to channel width quantization, two competing contributors impact mismatch: as FIN number becomes smaller mismatch due to MGG likely play an important role which increases threshold voltage mismatch, whereas FIN number becomes larger, systematic variation becomes the main factor, which also increases threshold voltage mismatch.

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.

Gate Stack Resistance and Limits to CMOS Logic Performance

The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON), high K metal gate first stacks (GF), and high K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Measured noise data supports this decomposition. Gate resistance increases at advanced nodes and affects typical logic performance of a 20 nm replacement gate technology.

Gate stack resistance and limits to CMOS logic performance

The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON) high-K metal gate first stacks (GF) and high-K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Gate resistance increases at advanced nodes and affects typical logic performance of a 20nm replacement gate technology.