Richard Q. Williams

Record RF performance of 45-nm SOI CMOS Technology

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fTs of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fTs are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond

FinFET SRAM for high-performance low-power applications

The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below-GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the read/write performance, reduce standby leakage, and mitigate process (VT) variability. The application of the technique to stacked read transistors in 8-T SRAM is also discussed.

Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored

SOI CMOS Technology with 360GHz f T NFET, 260GHz f T PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fTs of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging device modeling features and their enhancements. At nominal Lpoly, floating-body NFET and PFET demonstrate peak fT of 300GHz and fMAX of higher than 350GHz with excellent model-to-hardware accuracy. For precision analog circuit design, body-contacted (BC) FETs and various passives are offered, and their performance and modeling accuracy are co-optimized to push the technology limit and achieve state-of-the-art circuits, e.g., 28Gb/s serial link transceiver and LC-tank VCO operating at higher than 100GHz.

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield

We study the yield improvements of mixed/split gate designs in 45 nm FinFET technology. The original contributions of this paper are: fast statistical analysis for FinFET designs including 6T and 8T column- decoupled designs, and the proposed low-voltage 6T- column-decoupled SRAM cell using stacked_and FinFET devices. Sensitivities of the cell yield to device design uncertainties and process variations are evaluated. Statistical analysis indicates that column-decoupled cells can help lower the stability requirement on the cell beta ratio and hence relax the design limitations with FinFET technology such as quantization penalties. Furthermore, physical cell image diagrams show that the 6T-decoupled cell suffers very small area penalties compared to the traditional double gate designs. Fast statistical analysis techniques are used to estimate yield trend. Numerical device/circuit mix-mode simulations support the predicted trends. Threshold voltage variations due to random dopant fluctuations are estimated using a macroscopic modeling method. The impact of fin-height variations is also evaluated.

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges

This paper reviews the status and challenges of the modeling partially-depleted silicon-on-insulator transistors. Many challenges stem from the floating-body potential, which offers advantages in terms of performance and leakage, but presents complex electrical behavior. Circuit simulator considerations and the importance of model standardization are also highlighted.