Tackhwi Lee

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

Ultrathin HfO2 (equivalent oxide thickness=1.1nm) metal-oxide-semiconductor capacitors on n-GaAs substrate with germanium passivation

We present the capacitance-voltage characteristics of TaN∕HfO2∕n-GaAs metaloxide-semiconductor capacitors, with an equivalent oxide thickness (EOT) of 10.9A, low frequency dispersion, and a low leakage current density (Jg) of ∼10−6A∕cm2 at ∣VG−VFB∣=1V. Physical vapor deposited high-k dielectric film (HfO2) and a thin germanium (Ge) interfacial control layer (ICL) were used to achieve the low EOTs. As postdeposition annealing (PDA) time increases beyond a critical point, EOT and Jg also abnormally increase due to the degradation of the interface between Ge and GaAs surface, which was well indicated in electron energy loss spectroscopy, energy dispersive x-ray spectroscopy, and transmission electron microscopy analyses. Results indicate that a thin Ge ICL, optimized conditions for PDA, as well as high-k material (HfO2) play important roles in allowing further EOT scale down and in providing a high-quality interface.

Metal gate-HfO2 metal-oxide-semiconductor capacitors on n-GaAs substrate with silicon/germanium interfacial passivation layers

In this letter, the authors present the capacitance-voltage and current-voltage characteristics of TaN∕HfO2∕n-GaAs metal-oxide-semiconductor capacitors with thin silicon and germanium interfacial passivation layers (IPLs). Physical vapor deposition high-k dielectric films and silicon/germanium IPLs were deposited on GaAs substrate which has been cleaned with HCl and (NH4)2S solutions. Equivalent oxide thickness (EOT) of 12.5A and dielectric leakage current density of 2.0×10−4A∕cm2 at ∣VG−VFB∣=1V with low capacitance-voltage frequency dispersion have been obtained. The results indicate that the use of a thin silicon/germanium IPL assists in scaling EOT below 13A, while improving the quality of the interface.

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy₂O₃-incorporated HfO₂ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy₂O₃ laminated HfO₂ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO₂. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy₂O₃/HfO ₂ multimetal stack oxide n-MOSFET such as lower V_T, higher drive current, and an improved channel electron mobility are reported. Dy₂O₃/HfO₂ sample also shows a better immunity for V_t instability and less severe charge trapping characteristics. Two different rationed Dy ₂O₃/HfO₂ and HfO₂ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D_it), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility

Hafnium Titanate bilayer structure multimetal dielectric nMOSCAPs

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bilayer multimetal oxide dielectric has been developed for high-performance CMOS applications. Ultrathin equivalent oxide thickness (/spl sim/8 /spl Aring/) has been achieved with increased effective permittivity (k/spl sim/36). Hysteresis was significantly reduced using the bilayer dielectric. Top TiO/sub 2/ layer was found to induce effective negative charge from the flatband voltage shift. Leakage current characteristic was slightly higher than control HfO/sub 2/, and this is believed to be due to the lower band offset of TiO/sub 2/. However, the interface state density of this bilayer structure was found to be similar to that of HfO/sub 2/ MOSCAP because the bottom layer is HfO/sub 2/. These results demonstrate the feasibility of new multimetal dielectric application for future CMOS technology.

Device characteristics of HfON charge-trap layer nonvolatile memory

The authors studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al2O3/HfON/SiO2/p-Si structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH3 nitridation technique to incorporate nitrogen into the thin HfO2 layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler–Nordheim tunneling current to increase the erase and programming speed. The trap level energy in the HfON layer was calculated by using an amphoteric model.

Systematic analysis of silicon oxynitride interfacial layer and its effects on electrical characteristics of high-k HfO2 transistor

High-k hafnium oxide dielectric metal-oxide-semiconductor field-effect transistors with several physical thicknesses of silicon oxynitride interfacial layers were investigated to understand the relationship of their effects to electrical properties. Both flatband voltage and threshold voltage were negatively shifted with reduction of leakage current density as the thickness of silicon oxynitride interfacial layer increased. Charge pumping measurement revealed that the density of interface states were proportional to the physical thickness of the interfacial layer. The large amount of positive charge and interface state density for the thick interfacial layer affected the effective channel electron mobility, resulting in 20% of low-field peak mobility degradation. In addition, less stress immunity under stress was observed when silicon oxynitride interfacial layer increased.

Optimization and reliability characteristics of TiO/sub 2//HfO/sub 2/ multi-metal dielectric MOSFETs

Optimization of TiO/sub 2//HfO/sub 2/ bi-layer dielectric MOSFETs and their breakdown behaviors have been investigated for the first time. As the ratio of TiO/sub 2/ top layer increases, reduced EOT, reduced hysteresis, and improved transistor characteristics with increasing electron and hole mobility are observed. Distribution of a two-step breakdown characteristics suggest the breakdown occurs first in the HfO/sub 2/ bottom layer.

Mechanism of VFB/VTH shift in Dysprosium incorporated HfO2 gate dielectric n-Type Metal-Oxide-Semiconductor devices

The authors discuss temperature-dependent dysprosium (Dy) diffusion and the diffusion-driven Dy-silicate formation process in Dy incorporated HfO2. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO2 interfaces since the VFB shift in Dy2O3 is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment and becomes dominant in controlling the VFB/VTH shift during the high temperature annealing in the Dy–Hf–O/SiO2 gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility.

Reduced Gate-Leakage Current and Charge Trapping Characteristics of Dysprosium-Incorporated

The higher effective barrier height of Dy2O3 , which is around 2.32 eV calculated from the Fowler-Nordheim plot, accounts for the reduced leakage current in Dy-incorporated HfO2 n-type metal-oxide-semiconductor devices. The lower barrier height of HfO2 characterizes the increasing electron-tunneling currents enhanced by the buildup of hole charges trapped in oxide, which causes a severe increase in the stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy-incorporated HfO2 inhibits a further increase in the electron tunneling from the TaN gate, and trapped holes lessen the hole-tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO2 dielectric demonstrate the high dielectric-breakdown strength by weakening the charge trapping and the defect generation during the stress.