Van H. Le

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

Tunneling Field Effect Transistor (TFET) has attracted interest due to its steep-SS prospects [1]. Although a number of sub-60mV/dec TFETs were demonstrated [2], many failed to realize this feat due to non-optimized geometry, material choice [3], and material defects [4, 5]. In this paper, we clearly distinguish the requirement for i) geometry, ii) semiconductor BTBT characteristics, iii) semiconductor defects and iv) oxide interface defects. Using Ge as a case study, multi-temperature characterization of experimental PIN diodes is used to separate bulk properties from the interface effects, calibrating the models for BTBT, trap-assisted-tunneling (TAT) and SRH. The measured BTBT characteristic of a material is as important as the effect of defects; even a zero-defect TFET using the calibrated Ge material requires thin body and thin oxide. Bulk SRH and TAT is found to be a less critical issue for thin body TFETs, whereas interface defect density ~1012cm-2 is low enough to only degrade TFET SS <;10mV/dec. The method of current component segmentation using multi-temperature short-intrinsic PIN diodes is essential for evaluation of materials for TFETs.