Shuo-Mao Chen

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

Effects of germanium and carbon coimplants on phosphorus diffusion in silicon

The authors have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultrashallow n+∕p junction formation using phosphorus, carbon, and germanium coimplants, and spike anneal. Their experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. They find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion by trapping more excess interstitials. This conclusion is consistent with the end-of-range defects calculated by Monte Carlo simulation and annealed carbon profiles.

Relaxation-Free Strained SiGe with Super Anneal for 32nm High Performance PMOS and beyond

The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved