Shyng-Tsong Chen

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

BEOL Integration of Highly Damage -Resistant Porous Ultra Low-K Material Using Direct CMP and Via-first Process

We have demonstrated porous ultra low-K (ULK)/Cu interconnect integration using via first integration scheme and a direct ULK CMP process. The key features of the damage-resistant porous ULK material were novel material chemistry, a higher carbon concentration (15.4 atm%) and an improved pore structure. These improved features of the new ULK material enabled superior process-induced dielectric material damage during patterning etch, resist strip, and ULK direct CMP. Interconnect structures fabricated using the conventional ULK material showed high short leakage currents and open failures due to moisture uptake. The integrated structures of the new, robust porous ULK material exhibited good electrical properties. The target capacitance values have been achieved for future porous ULK/Cu interconnects

Ash-induced modification of porous and dense SiCOH inter-level-dielectric (ILD) materials during damascene plasma processing

Modification of low-k dielectric materials during photoresist plasma stripping was examined using a variety of analytical techniques. These techniques were initially applied to blanket wafers and were subsequently applied to both specially-designed test structures and product structures on patterned wafers. Results of these experiments are presented and analyzed.

Enhanced process control of pitch split double patterning by use of CD-SEM critical dimension uniformity and local overlay metrics

A Critical Dimension-Scanning Electron Microscopy (CD-SEM) technique for determination of both the CD width and the local overlay between individual pitch split layer 1 and layer 2 is employed for measurement on electrical device test structures and nearby in-die metrology sites. Measured overlay correlation studies by varying radial distances of in-die overlay metrology sites to the electrical test structures within the field show distance threshold effects. The lack of overlay vector correlation above a distance threshold is confirmed by examining the correlation of the electrically measured capacitance difference between the pitch split layers and the measured overlay at different in-die site locations. This methodology is applied to examine pitch split process improvements.

Optimization of pitch-split double patterning photoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Multilevel integration of patternable low-κ material into advanced Cu BEOL

In this paper, we wish to report, for the first time, on a simple, low-cost, novel way to form dual-damascene copper (Cu) on-chip interconnect or Back-End-Of-the-Line (BEOL) structures using a patternable low dielectric constant (low-κ) dielectric material concept. A patternable low-κ dielectric material combines the functions of a traditional resist and a dielectric material into one single material. It acts as a traditional resist during patterning and is subsequently converted to a low-κ dielectric material during a post-patterning curing process. No sacrificial materials (separate resists or hardmasks) and their related deposition, pattern transfer (etch) and removal (strip) are required to form dual-damascene BEOL patterns. We have successfully demonstrated multi-level dual-damascene integration of a novel patternable low-κ dielectric material into advanced Cu BEOL. This κ=2.7 patternable low-κ material is based on the industry standard SiCOH-based (silsesquioxane polymer) material platform and is compatible with 248 nm optical lithography. Multilevel integration of this patternable low-κ material at 45 nm node Cu BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure.