Siong Chiew Ong

Embedded Wafer Level Packaging for 77-GHz Automotive Radar Front-End With Through Silicon Via and its 3-D Integration

In this paper, a 77-GHz automotive radar sensor transceiver front-end module is packaged with a novel embedded wafer level packaging (EMWLP) technology. The bare transceiver die and the pre-fabricated through silicon via (TSV) chip are reconfigured to form a molded wafer through a compression molding process. The TSVs built on a high resistivity wafer serve as vertical interconnects, carrying radio-frequency (RF) signals up to 77 GHz. The RF path transitions are carefully designed to minimize the insertion loss in the frequency band of concern. The proposed EMWLP module also provides a platform to design integrated passive components. A substrate-integrated waveguide resonator is implemented with TSVs as the via fences, and it is later used to design a second-order 77-GHz high performance bandpass filter. Both the resonator and the bandpass filter are fabricated and measured, and the measurement results match with the simulation results very well.

A novel die to wafer (D2W) collective bonding method for MEMS and electronics heterogeneous 3D integration

A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 × 3 mm2 and 8 inch ASIC wafers. The new package design was proposed in order to reduce the parasitic effect by attaching the released MEMS dice directly to the pads on an ASIC wafer. Two different types of MEMS devices having combs structure and a beam structure were used in order to confirm the minimal change in the MEMS functionality before and after D2W bonding. The ASIC wafer consisted of non functional circuit with pads and the daisy chain for measuring the electrical resistance and interconnection lead-out. With the new method by utilizing both the standard pick and place machine and the wafer bonder, ~ 800 numbers of functional MEMS dice were bonded to ASIC by low temperature D2W collective bonding at 200 degC for 2 minutes having an alignment tolerance less than 10% in 150 μm pitch with pad size of 75 μm. In this approach, the bonding time has been reduced by more than 50% in comparison with the conventional D2W bonding with flip chip bonder and performance of the package was improved by direct interconnection and the yield was improved by bonding with Known Good Dice.

Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking

An IMC based low temperature solder <200 °C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.

Thin die stacking by low temperature In/ Au IMC based bonding method

Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200˚C forming robust intermetallics (IMC) joints with high re-melting temperature (>300˚C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90˚C (chip/wafer) for 20sec and 180/180˚C for 5mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120~330N (23.5~38.8MPa). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260˚C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.

Development of thin film dielectric embedded 3D stacked package

In this paper, a process for embedding and interconnecting three dimensional (3D) thin chips stacked in multilayer dielectric at wafer level is presented. Chips of different dimensions are thinned to 30 μm thickness using conventional back-grinding and singulated by dicing. Thin chips of different dimensions were then stacked onto a silicon carrier and embedded in multilayer of pre-formed photo-dielectric film using a vacuum lamination process. Photo-lithography process was used to develop the micro-vias in the dielectric film and thin film metallization is used to form interconnection between the vertically stacked chips. Under bump metallization is processed on the fan-out region of the thin film metallization lines for board level connectivity. Finally, the silicon carrier is removed to release the embedded 3D stacked package. The embedded 3D stacked package fabricated has a thickness of 110 μm and electrical measurements shows good electrical connectivity between the 2 chips stacked and the fan-out metallization lines.

A 135GHz slotline bandpass filter using silicon/membrane technology

This paper presents the design and implementation of a second-order 135GHz bandpass filter (BPF) constructed on a thin suspended membrane structure. The BPF is built by cascading two U-shape slotline resonators formed on the ground plane. The input and output coupling are achieved by the microstrip line to slotline transition on the other side of the substrate. The unloaded quality (Q) factors of both I-shape and U-shape resonator due to the radiation, material and conductor loss are studied. The BPF is fabricated and measured, and it demonstrates a good agreement between the simulation and measurement results.