Cheryl S. Selvanayagam

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of silicon (~2.5 times10-6/degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moores (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10-6/degC) is a few times higher than that of silicon (~2.5x10-6/degC). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moores (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Modeling Stress in Silicon With TSVs and Its Effect on Mobility

With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3-D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5 × 10-6/°C) and silicon (2.5 × 10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this paper, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for: 1) designing substrates with TSVs such that mobility in the active devices are not affected by the presence of TSVs, and 2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

Through Silicon Via interposer for millimetre wave applications

A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivity. However, at millimetre wave (mmWave) frequency range, especially above 50GHz, in addition to the insertion loss, the return loss due to impedance mismatched becomes significant. These losses become a serious setback for the Si Interposer for the mmWave applications. To overcome these losses, polymer cavity formed in the Si substrate with TSV is developed. The polymer has lower loss tangent and lower dielectric constant than Si. These properties can help to reduce the insertion loss and the return loss. Depending on the requirement, multiple set of TSV can be formed on the polymer cavity to provide higher interconnect density. From the simulation results, the new polymer cavity TSV at 100GHz have an insertion loss and return loss of ∼0.2dB and less than −25dB, respectively. On the other hand, conventional high resistivity TSV has an insertion loss and return loss of ∼1.4dB and more than −10dB, respectively, at the same frequency. For higher frequency range, the performance of the polymer cavity TSV is approximately consistent, but the conventional TSV deteriorated drastically. In this paper, the design, fabrication process and the measurement results are presented. The prototype polymer cavity TSV via-line-via test vehicle has a measured insertion loss of less than 1dB and a return loss of better than −10dB through the frequency range up to 110Gz.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance [1]. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5×10−6/°C) and silicon (2.5×10−6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication [2, 3, 4]. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

FCBGA Package With Through Silicon via (TSV) Interposer

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Modelling stress in silicon with TSVs and its effect on mobility

An IMC based low temperature solder <200 °C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.

Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this paper, piezoresistive stress sensors were used to evaluate the stresses in device wafer after wafer bumping process, such as under bump metallization fabrication, dry-film process, and solder bumping. For the stress evaluation, n-type piezoresistive stress sensors were fabricated on p-type (100) silicon wafer and then sensors were calibrated to determine piezoresistive coefficients. The calibrated sensor wafers were finally used to measure residual in-plane stresses at the surface of device wafer. Due to the growing demand of portable and handheld devices, the reliability of electronic packages with Pb-free solder under drop impact condition has become an issue of concern. This paper aims to measure the real-time stress in an ultrathin die during a drop test to ascertain whether die cracking is a possible problem when dealing with 50-μm-thick dies. The advantages of these stress data are that they: 1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and 2) are important to enhance survivability during wafer bumping, handling and packaging.