Sujatha Sankaran

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Integration of chemical vapor deposition Al interconnects in a benzocyclobutene low dielectric constant polymer matrix: A feasibility study

Results are presented from a proof-of-concept study that examined the integration of damascene-processed thermal chemical vapor deposited (TCVD) aluminum (Al) interconnects in a benzocyclobutene (BCB) polymer matrix. In a first phase, the study identified baseline deposition conditions for the formation of structurally and chemically compatible blanket Al/titanium nitride (TiN)/BCB stacks on two types of blanket BCB substrates utilized to simulate the actual surfaces encountered in typical damascene processing: (1) blanket BCB films capped with a silicon dioxide SiO2 layer (SiO2-BCB), and (2) plasma reactive ion etched blanket BCB films. The TiN diffusion barrier was grown in two stages. A first (bottom) layer was deposited by physical vapor deposition (PVD), followed by a CVD-grown top layer. The resulting TCVD Al/CVD TiN/PVD TiN/BCB stacks were stable under thermal stressing up to 325 °C for 1 h. In a second phase, an optimized TCVD Al process flow was developed for void-free filling of TiN-coated 320-n...

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.