Sunil Wickramanayaka

Wafer level underfill study for high density ultra-fine pitch Cu-Cu bonding for 3D IC stacking

A wafer level under-fill (WLUF) process for ultra-fine Cu-Cu bonding is developed. Under-fill is applied as pre-applied under-fill then planarized the surface. The methodology used for surface planarization (bit grinding) and surface treatment (H2 plasma) are fond to be important in the surface preparation and activation. Underfill material needs to have sufficient hardness and adhesion to the wafer to survive during bit grinding process. Again, it must not get cured during plasma treatments before bonding is carried out. DOE is carried out with four different WLUF materials and one capillary under-fill material. Tests were carried out with a test vehicle having 5 um diameter and 10 um pitch. Results showed only one material could pass through all those requirements.

6um Pitch High Density Cu-Cu Bonding for 3D IC Stacking

For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain size), (4) certain levels of roughness and (5) even the Cu pillar with or without TSV in the wafer. In this paper, test vehicle with dia3um and pitch 6um TSV 20um thin wafer are design and fabricated. The test vehicle is used to study above major bonding contributors. Solid Cu-Cu interconnects are demonstrated with both Chip to chip (C2C) and Chip to wafer (C2W) process. The developed process is promising for high density I/O (<;10um pitch) low temperature (200°C) Cu-Cu bonding for 3D stacking.

Process development of 10μm pitch Cu-Cu low temperature bonding for 3D IC stacking

A low temperature <;200°C Cu-Cu bonding process is developed for 3D IC stacking application. To prepare and activate good copper surface, three planarization processes and two surface treatment methods are studied in details and compared. Best surface treatment method is identified. It is found that good Cu-Cu direct bonding with high shear strength is achieved by the developed process and verified by the cross sectional structure. Low temperature Cu-Cu bonding for 3D IC applications is demonstrated by a high density Cu bump array structure with 10 μm pitch and 5 μm diameter. Chip-to-chip bonding approach is used for 3D IC stack bonding. Final cross sectional and daisy chain electrical measurement showed good connectivity of micro bump joints.

Chip to wafer hermetic bonding with flux-less reflow oven

In this study, it is shown that temporary tacking (without flux and temporary tack materials) is feasible to temporary tack Cu/SnAg or SnAg sealing ring onto Cu sealing ring at the bottom wafer. The temporary tacked samples were reflowed in a formic acid environment and this allowed the removal of the native oxide of solder. The removal of oxide provides a good solder joints formation during reflow [4]. Vacuum reflow with formic acid and load of 20g per unit showed good sealing results. Helium leak test for chip on silicon substrate was carried out. The results indicated the leak rate at the level of ≤ 5×10−8 atm cc/s Helium can be achieved. Chip on wafer (CoW) bonding with hermetic sealing was demonstrated on 8″ wafer with cavity.

Al-Ge Diffusion Bonding for Hermetic Sealing Application

The high-temperature requirement of Al-Ge eutectic bonding stands as a major obstacle to its wider acceptance for hermetic sealing application in the microelectromechanical systems packaging industry, in particular for temperature-sensitive devices. It has been demonstrated that a reduction in bonding temperature is feasible without compromising the hermeticity. The change in the mode of bonding from eutectic to solid-state diffusion did not have a dramatic impact on the bonding quality. However, this resulted in a substantial increase in bonding time. The shear strength also deteriorated as a result of the decrease in thickness of the reaction interface. However, the shear strength still complied with military standards. It has been confirmed that a hermetic seal could still be achieved without any solidification occurring at the interface. This is feasible since the interdiffusion coefficients of Al in (Ge) phase and Ge in (Al) phase are closer and are comparable to diffusion between solid-solution phases of identical metals such as in Au-Au, Cu-Cu, and Si-Si bonding, which are generally used for such hermetic sealing application. An appropriate stacking mechanism for Al-Ge diffusion bonding is identified to overcome the limitations with respect to surface topography.

Thin-Film Magnetic Inductor for Integrated Power Management

This paper presents the design considerations for thin-film magnetic power inductors for integrated voltage regulator (IVR). Optimum design parameters for solenoid inductors are arrived at that maximize key performance metrics such as quality factor, inductor efficiency, inductance density, and operation frequency. A fabrication approach to integrate the solenoid inductor with thin-film magnetic material is presented. Finally, electrical characterization of a set of test inductors that were fabricated is carried out and the results such as inductance, quality factor, DC resistance are presented.

Stealth Dicing Challenges for MEMS Wafer Applications

In our digital world, microelectromechanical system (MEMS) are here to stay and will open the doors for the next exciting wave in the advancement of technology such as the Internet of Things (IoT). The MEMS devices in wafer forms are fabricated in minute details and eventually singulated into individual units to act as sensing or actuation elements in various applications such as accelerometer and gyroscopes for navigation, in wireless mobile and smart car applications. Handling of such MEMS device requires overcoming many challenges in both fabrication and assembly. Singulation of MEMS device with fragile and sensitive structures is one of the many assembly challenges. In fact, most devices are capped to protect its active moving components that maybe damaged when using conventional singulation method that is by mechanical dicing wherein water splashes or pressure is unavoidable. With the introduction of stealth laser dicing, where micro damage is created internally and through several layers of this damages creates a propagation to eventually separate the wafer upon forced expansion through tape, it became possible for a dry process singulation without damaging the fragile components. However, stealth dicing leverages on infrared waves being transparent only and able to penetrate through smooth surface silicon wafers and at certain resistivity or level of doping to create internal damage on the work piece. As such, stealth dicing process may have difficulty to handle saw street with metallization, heavily doped or high resistivity wafer as in the case of SOI wafer and deep trenches that may surface in some MEMS devices. This created limitations for MEMS designs, processes and materials selection that may not be limited to the active region alone but as well as on the dicing saw street. In this paper we will conduct stealth dicing study on various types of wafer configuration and thus making a clearer assembly process for next generation of mobile applications and the fast growing market of IoT.

Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder

Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.

Mitigation of thin wafer handling issues in TSV (Through Silicon Via) fabrication for advanced packaging applications

Present study focuses on various thin wafer handling issues associated with via-last TSV fabrication integration schemes. Thin wafer handling methodology play very key role in any successful TSV interposer fabrication. Zonebond TBDB method is selected for this evaluation and critically analysed issues encountered in various fabrication steps like PECVD, PVD, etching, curing and CMP processes. Thin TSV wafer fabrication is always challenging as thin wafers are instable and more prone to failures in various fabrication environments. Hence it is timely to establish robust thin wafer handling schemes that promote seamless TSV interposer wafer fabrication. Extensive TBDB and process integration DOE has been conducted to mitigate these issues.

Ultra-fine pitch Cu-Cu bonding of 6μm bump pitch for 2.5D application

Ultra-fine pitch (6μm) interconnects are essential for high-end application-products that demands high speed and high bandwidth inter-chip communication. Achieving Cu-Cu bonding with such a fine pitch is challenging since bond time is too long and bond interface gets easily oxidized. Throughput issue associated with long-bonding time is solved by using 2-step bonding procedure where first step is a temporary bonding and second step is a permanent bonding using a gang bonder. Gaseous formic acid is used to remove surface oxide on Cu surface and wafer level pre applied underfill is used as a tacking material in temporary bonding. Bonding is carried out with dies having 500,000 interconnects and the results show excellent bonding and electrical properties.