Suresh D. Kadakia

Multilayer glass ceramic substrate design for SS-1 supercomputer

The SS-1 supercomputer system requires a packaging technology which supports high signal propagation speed and dense wiring for a faster clock cycle time. This has been achieved by a packaging technology and a design which provides the right TOF, matching impedance and conductors with lower resistance. A number of technological advancements have been made from ES/9000 TCM to meet the supercomputer system requirements. These changes are discussed in detail and compared to the state-of-the-art technology of ES/9000. The substrate design, the thin film, and the interposer are described.<<ETX>>

Design trade-offs in high performance packages

The objective of this paper is to focus on design considerations and on design methodology for high performance packages. Discussion will be restricted to Single Chip Packages only. Wirebond and Flip chip packages in Pin Grid and Ball Grid I/Os are described here. As shown here design considerations are primarily driven by customer input followed by electrical modeling and process modeling to guarantee performance and cost. The electrical performance of the package is analyzed by evaluating the parasitic parameters.

Advanced design and modeling for manufacturability of a hybrid MCM package

The objective of this paper is to focus on manufacturability aspects of the MCM package through advanced design and modeling techniques. Two types of modeling are discussed: electrical and process. Use of electrical modeling to enhance manufacturability is demonstrated. Process modeling is driven by the requirements to maximize yield. A Poisson model which relates the product complexity and process characteristics to electrical yield are discussed. Three phases of advanced design techniques, namely cube design, substrate design and thin film design are shown to reduce cycle time and also manufacturing defects. >

Process Modelling And Advanced Design Techniques For A Multi-chip Hybrid Package

Packaging technology has seen the familiar trends of the electronic industry with increasing size and wireability requirements. Along with those requirements come new materials to improve performance and tighter groundrules to increase interconnectivity. These requirements and new materials must be understood in order to insure manufacturability of new products for the marketplace. In IBM, this path is seen in the migration of Thermal conduction module (TCM) made with AI203 (Alumina) ceramic to the new ES9000 T C M made with glass-ceramic (G/C) and thin film. This paper prescnts process modelling and design techniques that assisted IBM in the manufacturing success of this new hybrid technology. The ES9000 T C M is a 127mm square module made of Corderite glass-ceramic that is 63 layers thick. It has up to 121 chip sites with decoupling capacitors a t the corners of the chips (figure I). There are 2772 1/0 pins for power and signal and this substrate can cool up to 2000 watts with its water cooled cap (figure 2). This substrate supports 14 planc pairs of wiring that can have roughly 400 meters of interconnect wiring. Key features include partial thin film redistribution and buried engineering change (EC) wiring planes to assist in minor EC capability as well as repair. Fig.1. ES/9000 glass-ceramic substrate Fig.2. ES/9000 Module Assembly