Susumu Shuto

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-/spl mu/m, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C/sub ferr/ is larger than reference-cell capacitance C/sub MOS/. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme.

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS achieves 37 ns random-access time and 80 ns read/write cycle time at 3.3 V.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

Impact of passivation film deposition and post-annealing on the reliability of flash memories

This paper presents the impact of the passivation film deposition with various compositions and structures on the reliability of tunnel oxide in flash memories. The enhancement of the tunnel oxide degradation strongly depends on the refractive index of P-SiON passivation film. This result means that there is a correlation between the water resistibility of the passivation film and the tunnel oxide degradation induced by the passivation film deposition process. Moreover, the effect of post-annealing after passivation film deposition is discussed. The electron trap density is increased at the beginning and then decreased during post-annealing. The time constant of this phenomenon strongly depends on the refractive index of the passivation film. We propose the water-related electron trap model to explain the results.

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, a two-way metal cell-plate line and a cell-plate line shared with 16 cells, reduce cell-plate-line delay to 7 ns and reduce plate drive area to 1/5. The total cell-plate-line delay, including cell transistor delay due to eight cells in series, is reduced to 15 /spl mu/s, in contrast to 30-100-ns delay of the conventional FRAM. The die size is reduced to 86% that of the conventional FRAM by reduction of the plate driver area and sense amplifier area, assuming the same memory cell size. A prototype 16-kb chain FRAM chip was fabricated using 0.5 /spl mu/m rule one-polycide and two-metal CMOS process. The memory cell size was 13.26 /spl mu/m/sup 2/ using a 3.24-/spl mu/m/sup 2/ capacitor. Thanks to the fast cell-plate-line drive, the chain FRAM test chip has achieved the fastest random access time, 37 ns, and read/write cycle time, 80 ns, at 3.3 V so far reported. The chain FRAM has also realized V/sub dd min/ of 2.3 V and 10/sup 10/ read/write cycles.

Read disturb degradation mechanism for source erase flash memories

The read disturb degradation caused by source erase is studied. The anomalous Vth shift of about 1.0 V due to electron trapping is observed during read disturb. Vth shift due to electron trapping is more serious for high speed erase device. However, this Vth shift can be suppressed by using lower source voltage for erase.

An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)

An extremely small NAND-structure cell of 1.13 µm2 per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 991], has been developed in 0.4 µm technology. The chip size of a 64 Mb NAND electrically erasable and programmable read only memory (EEPROM) using this cell is estimated to be 120 mm2, which is 60% that of a 64 Mb DRAM. In order to realize the small cell size, a 0.8 µm field isolation is used. A negative bias of -0.5 V to the P-well of the memory cell is applied during writing. In addition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in comparison with the conventional 5 V scheme. As a result, it is expected that with this technology, 106 write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.