Yoshinori Kumura

Ferroelectric Properties of Pb(Zi, Ti)O3 Capacitor with Thin SrRuO3 Films within Both Electrodes.

Ferroelectric properties of a Pb(Zi, Ti)O3 (PZT) capacitor with thin SrRuO3(SRO) films within both electrodes were investigated in detail. Thin SRO films of 10 nm thickness markedly improve the electrical performance, such as switching charge (Qsw), saturation characteristics of the hysteresis curve and imprint performance even at an elevated temperature. It should also be noted that there was no Qsw degradation after 5×1010 read/write cycles at 5 V. No leakage current increase after the test was observed. The results of transmission electron microscope (TEM) and electron dispersive X-ray (EDX) analyses also showed that there is no diffusion of either Sr or Ru in the PZT film. The Qsw increase can be explained by the model in which excess oxygen ions existing in the SRO films drift into the PZT due to the external electric field where they fill the oxygen vacancies in the PZT near the interfaces. We confirmed that the proposed electrode structure was a key to realizing highly reliable ferroelectric random access memories (FRAMs).

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

A novel characterization method to monitor process damage for transistors

The most appropriate method to evaluate the process damage is proposed. FeRAM process is used as a damage source. The degradation of the drain current of long-channel MOSFET is larger than that of short-channel MOSFET, although long-channel MOSFET has been believed to be more robust. In the case of short-channel MOSFET, the drain current is limited by saturation velocity, and thus the mobility degradation caused by the process damage has a smaller influence. On the contrary, in the case of long-channel MOSFET, the drain current is not limited by saturation velocity, which leads to the degradation of the drain current owing to the mobility reduction caused by the process damage of the FeRAM capacitor process. These results suggest that the most accurate method for evaluating the process damage is to monitor the degradation of the drain current of long-channel MOSFET.

Key process technology for high density 64M FeRAM and beyond

Difficulty to achieve high density FeRAMs with sub-micron ferroelectric capacitors is widely understood due to damage to the capacitors. Key process techniques such as high quality ferroelectric film deposition, electrode preparation, capacitor RIE and hydrogen barrier structure formation are introduced for 64M FeRAMs with sub micron high reliability PZT capacitors.