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Dive into the research topics where Uwe Griebenow is active.

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Featured researches published by Uwe Griebenow.


Archive | 2010

HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED AT DIFFERENT PROCESS STAGES OF A SEMICONDUCTOR DEVICE

Jan Hoentschel; Sven Beyer; Thilo Scheiper; Uwe Griebenow


Archive | 2010

Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices

Jan Hoentschel; Andreas Kurz; Uwe Griebenow; Thilo Scheiper


Archive | 2013

Transistors Comprising High-K Metal Gate Electrode Structures and Embedded Strain-Inducing Semiconductor Alloys Formed in a Late Stage

Uwe Griebenow; Jan Hoentschel; Thilo Scheiper; Sven Beyer


Archive | 2010

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

Jan Hoentschel; Sven Beyer; Uwe Griebenow


Archive | 2012

ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION

Jan Hoentschel; Uwe Griebenow; Maciej Wiatr


Archive | 2013

FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION

Thilo Scheiper; Sven Beyer; Uwe Griebenow; Jan Hoentschel


Archive | 2010

Optical signal transfer in a semiconductor device by using monolithic opto-electronic components

Uwe Griebenow; Sven Beyer; Thilo Sheiper; Jan Hoentschel


Archive | 2010

Contact bars with reduced fringing capacitance in a semiconductor device

Thilo Scheiper; Sven Beyer; Uwe Griebenow; Jan Hoentschel; Andy Wei


Archive | 2011

Technique for enhancing transistor performance by transistor specific contact design

Martin Gerhardt; Ralf Richter; Thomas Feudel; Uwe Griebenow


Archive | 2008

TECHNIQUE FOR STRAIN ENGINEERING IN SILICON-BASED TRANSISTORS BY USING IMPLANTATION TECHNIQUES FOR FORMING A STRAIN-INDUCING LAYER UNDER THE CHANNEL REGION

Uwe Griebenow; Kai Frohberg; Martin Gerhardt

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