T. Ngai

Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities

Double-gate FinFET (110) (110) and (100) (100} electron mobility (μ_e) and hole mobility (μ_h) are experimentally investigated for the following: 1) a wide range of boron and phosphorus fin doping concentrations and 2) a wide variety of gate stacks combining HfO₂, SiO₂, or SiON insulators with TiN or poly-Si electrodes. It is found out that, irrespective of fin doping and gate stack, (110) (110) μ_e is competitive with the (100)(100) μ_e, while (110)(110) μ_h is ≥ 2× higher than (100) (100) μ_h. Inversion μ_e and μ_h are independent of doping as long as the effective field/doping combination enables the screening of the depletion charge. Mobility degradation with doping is significantly lower in accumulation mode (AM) than in inversion mode (IM) such that, for heavily B-doped fins, AM hole mobility exceeds the IM electron mobility even in (100) FinFETs. In undoped fins, ALD TiN gate stress is observed to improve μ_e for both orientations without degrading μ_h.

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρ_c) extraction of 2×10^-8Ω cm² and 5×10^-9Ω cm² for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρ_c values. The results show the importance of such test structures to accurately extract ultralow ρ_c values relevant to sub-14-nm technology nodes.

New insights into SILC-based life time extraction

The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored at its maximum value rather than at any pre-defined, fixed voltage.

Enhanced performance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node

We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate stacks. These attributes constitute a simple non-planar cMOS integration sequence for enhancing future high performance technology nodes.

Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure

We demonstrate a 300mm wafer scale conformal contact process to achieve uniform ultra-low specific contact resistivity (ρ_c) for metal/high-k/n⁺Si (MIS) contacts. To achieve conformal contacts, we use a sidewall TLM (STLM) test structure that helps to minimize current crowding effect and variability. A systematic study is provided by varying doping density (N_D), high-k material (LaO_x, ZrO_x and TiO_x) and high-k thickness (t_d) to optimize ρ_c. The obtained ρ_c and its uniformity are found to be comparable with standard nickel silicide technology, with a possibility of further improvement by use of lower work-function metal.

Performance and variability in multi-V T FinFETs using fin doping

The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ~25 nm, >;1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation mode FinFETs. A VT modulation of ±0.25 V using fin B and P doping comes at the expense of 24% and 14% high field mobility penalty for NFET and PFET, respectively. For the same dose, Arsenic is found to modulate the VT more effectively than does Phosphorus. Basic modeling results show that for aggressively scaled (5 nm-wide) fins, the impact of single dopant atom on VT can be as high as 25 mV, severely challenging the viability of the technique towards the end of roadmap.

Contact resistance improvement by dielectric breakdown in semiconductor-dielectric-metal contact

We propose an approach for reduction of the contact resistance by inducing dielectric breakdown in a Si-dielectric-metal contact stack. We observe a 36% reduction in the contact resistance as well as an improvement in the uniformity in the distribution after dielectric breakdown. The results open up interesting device applications in complementary metal oxide semiconductor technology.

Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling

In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.

Performance and reliability investigation of (110) and (100) sidewall oriented MugFETs

In order to continue technology scaling to meet future performance needs, multi-gate field effect transistors (MugFETs), are currently under investigation. MugFETs can be fabricated on silicon-on-insulator (SOI), and they are especially attractive because their three-dimensional structure enables excellent immunity to short channel effects, without significant changes to conventional CMOS fabrication techniques. One MugFET design of interest is known as the FinFET, where a hard mask is placed on the top surface of a fin structure to decouple it from the sidewall device operation (fig. 1). FinFETs can be fabricated with either the (110) sidewall surface or (100) sidewall where the crystal orientation of the fin sidewalls can have an impact on mobility and thereby provide a mobility boost based on orientation (fig. 1) [1,2]. In planar CMOS technologies, orientation dependent mobility enhancement has been demonstrated through the use of hybrid orientation technology (HOT) [3,4]. Here, hole (h+) mobility (μeff) increases significantly when the channel orientation changed from Si(100) to Si(110). However, the electron (e−) mobility is severely degraded with the same orientation change. Therefore, there arises a need for HOT to take advantage of h+ μeff on Si(110) and e− μeff on Si(100). Our work demonstrates that the nMOS FinFET devices actually are not as severely degraded as planar nMOS, thereby mitigating the need to have orientation dependent CMOS FinFETs for μeff enhancement (fig. 2) [5]. However, a correlation of long channel mobility to short channel performance is necessary to confirm similar performance characteristics (fig. 3). Moreover, the implications of sidewall surface orientation on reliability issues such as hot carriers [6,7] and bias temperature instability [8,9] also need to be addressed. The surface orientation or fin structure may be more susceptible to degradation during stress. Possible causes include: Si interface bonds available for bond breakage [10] in the (110) plane, or structural properties that impact reliability differently than planar devices. In this work, we evaluate the dependence of FinFET sidewall orientation on performance (i.e., mobility and Ion/Ioff) and reliability, where hot carrier injection and BTI are evaluated.

Magnetron sputtering for the production of EUV mask blanks

Ion Beam Deposition (IBD) has been the primary technique used to deposit EUV mask blanks since 1995 when it was discovered it could produce multilayers with few defects. Since that time the IBD technique has been extensively studied and improved and is finally approaching usable defectivities. But in the intervening years, the defectivity of magnetron sputtering has been greatly improved. This paper evaluates the suitability of a modern magnetron tool to produce EUV mask blanks and the ability to support HVM production. In particular we show that the reflectivity and uniformity of these tools are superior to current generation IBD tools, and that the magnetron tools can produce EUV films with defect densities comparable to recent best IBD tool performance. Magnetron tools also offer many advantages in manufacturability and tool throughput; however, challenges remain, including transitioning the magnetron tools from the wafer to mask formats. While work continues on quantifying the capability of magnetron sputtering to meet the mask blank demands of the industry, for the most part the remaining challenges do not require any fundamental improvements to existing technology. Based on the recent results and the data presented in this paper there is a clear indication that magnetron deposition should be considered for the future of EUV mask blank production.