T. S. Chao

Scanning Probe Lithography of Self-Assembled N-(2-Aminoethyl)-3-aminopropyltrimethoxysilane Monolayers on SiO2 Surface

A new approach is introduced for the selective deposition of colloidal gold nanoparticles (AuNPs) onto the surface of unpatterned self-assembled monolayers (SAMs). The patterning of N-(2-aminoethyl)-3-aminopropyltrimethoxysilane (AEAPTMS) SAMs is realized by local field-induced bond breaking using scanning probe lithography (SPL) on a thin SiO2 surface. Different tip/sample biases were investigated to determine the bond breaking efficiency of AEAPTMS SAMs. It was found that bond breaking efficiency was limited by tunneling current through the thin SiO2 film so that both the tip bias and the tip scanning speed play important roles. AuNPs with negatively charged citrate surfaces were selectively anchored onto the unpatterned area via electrostatic force between AEAPTMS SAMs and AuNPs. Single-digit numbers of AuNPs anchored onto unpatterned AEAPTMS SAMs were demonstrated.

Novel Field-Induced Gray-Level Selective Patterning of Self-Assembled Aminosilane Monolayer on SiO2 Surfaces by Scanning Probe Bond-Breaking Lithography

We demonstrated a successful strategy for combining the straightforward scanning probe chemical bond-breaking lithography and self-assembly monolayer (SAM) techniques for constructing nanoscale architectural structures of gold nanoparticles (AuNPs) onto modified SiO2 surfaces. The hydroxyl-terminated surface of the sample substrate was modified by silanization with N-(2-aminoethyl)-3-aminopropyl-trimethoxysilane (AEAPTMS) molecules. Local-field-induced scanning probe bond-breaking lithography is adopted to selectively decompose the chemical bonds of AEAPTMS SAMs on aminosilane-modified SiO2 surfaces. From the experiments, a tip bias of less than 4.5 V cannot effectively decompose chemical bonds of AEAPTMS SAMs. Gray-level selectively patterned pictures were successfully observed on a modified 2.5-nm-thick SiO2 surface by applying dc voltage (2.5–5.5 V) between the atomic force microscopy (AFM) conductive tip and the SiO2 surface under ambient conditions. After the scanning probe selective decomposition of AEAPTMS SAMs, AuNPs with negative-charged citrate surfaces were selectively anchored in the selective patterning region via Coulomb electrostatic force. With proper control, it is considered that this novel technique can be applicable to the generation of various nanofabricated devices.

High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

In this paper, strain effects on silicon n-channel gate-all-around (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (Ion/Ioff >109) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.

Enhanced Subthreshold Slope and On-state Current in Tunneling Thin-Film-Transistors Using Metal Induced Lateral Crystallization

In this study, we propose a tunneling TFT fabricated by MILC method for the first time. The MILC tunneling TFTs demonstrate a lower subthreshold swing, ~232 mV/dec, than the other tunneling TFTs (T-TFTs) and a high on/off ratio > 10 6 at VDS=1V without any hydrogen related plasma treatment.

Investigation of Different Capping Layers and Strain Sources for SMT Process

Strain technique has emerged as a promising way for scaling down demand, including biaxial and uniaxial strain. For biaxial strain, a relaxed SiGe buffered layer fabricated by complex process may meet Ge out diffusion and dislocation penetration issues. For uniaxial strain, such as SiC S/D, contact etch-stop layer (CESL), and stress memorization technique (SMT) have been introduced.[1]-[3] Among these techniques, SMT possesses simpler process, and could be combined with other strain technique. Besides, Metal-InsertedPoly-Si (MIPS) combined with SMT could alleviate poly-Si depletion and achieve promoted mobility.[4][5] Recently, the influence of geometrical dependence and amorphization condition on the strain coupling was thoroughly investigated, since the thermal expansion characteristics of poly-Si gate as strain source play an important role for SMT.[6] However, the impact of capping layer properties and different strain sources on SMT fabrication still needs to be clarified. In this paper, different strain sources have been analyzed. And the impact of compressive and tensile nitride on performance, gate leakage, and hot carrier immunity is completely investigate.

Electric properties of SONOS memories with embedded silicon nanocrystals in nitride

Meng-Chien Hsieh, Tsung-Yu Chiang, Hua-An Dai, Chi-Ching Chen, Chen-Hao Chiang, Jia-Feng Wang, Yan-Jiun Lin, Ji-Ying He, Yan-Ning Chen, Tien-Sheng Chao, and Jenn-Fang Chen Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan 30050, Republic of China Phone: +886-3-5712121 ext. 56152 E-mail: markvipmail@yahoo.com.tw Abstract This study investigates the electrical properties of SONOS memories with embedded silicon nanocrystals (Si-NC) in nitride. The interface states at the SiO2/Si-substrate interface are identified by experiment and simulation. Embedded Si-NCs in nitride are confirmed as a formation of Si-quantum dots in nitride. The Si-NCs form quantum confined states above their conduction band (CB). The electron capture time of the Si-quantum dots states is increased during programming carriers. This mechanism reveals that the Si-quantum dots states are effortless to program, and that the electrons on these states after programming can be reserved more easily. Introduction Metal–oxide–semiconductor (MOS) memories with embedded Si-NCs and silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memories have recently attracted considerable attention because of their feasibility to overcome the limitations of conventional polycrystalline-silicon-based floating-gate memories [1]-[3]. Our previous works successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride [4]-[5]. This novel structure exhibits excellent characteristics in terms of larger memory windows, lower operation voltage, high P/E speed, and longer retention time. Nevertheless, the fundamental electric properties of this structure remain unknown. Experiments Figure 1 presents the device structure of the investigated samples. The SONOS memories with embedded Si-NCs are formed by ex situ deposition in nitride. Detailed growth conditions can be found elsewhere [4]-[5]. A series of various Si-NC size (no Si-NC (no_dot), small Si-NCs (small_dot), and large Si-NCs (dot)) are investigated in this work. The formation of Si-NCs was confirmed by atomic force microscopy [4]. Results and Discussion Figure 2 shows the capacitance-voltage (C-V) spectra (dashed line) of, and the corresponding simulation results (solid line) for, the investigated samples ((a) no_dot, (b) small_dot, and (c) dot). All of these samples have an additional capacitance peak in the positive bias region. The additional capacitance peak originates from the interface states at the SiO2/Si-substrate interface. The fundamental parameters (Dit (interface state density) and NQss (fixed oxide charges)) can be extracted by C-V simulation. The energy distributions of interface state density in the silicon band gap are extracted from C-V simulation, as shown in Fig. 3. These energy distributions are consistent with the previous non-annealing results [6]. The NQss are increased during the formation of Si-NCs. This result suggests that the embedded Si-NCs increase the number of trapping states in the oxide region, and trapping states are increased through enlarging the Si-NC size. Admittance spectroscopy was performed on these samples to investigate the emission time of the interface states. Figure 4 shows the temperature-dependent capacitance-frequency (C-F) spectra at bias of the additional capacitance maximum peak ((a) 2 V for no_dot, (b) 1.8 V for small_dot, and (c) 1.4 V for dot), and other biases of the additional capacitance peak exhibit the same temperature-dependent behavior. The dependence of the inflection frequency on temperature yields an activation energy (Ea) and a capture cross section (σ), as indicated in Table 1 (Ea, σ, and Ea from simulation). The similarity between the experimental activation energy and the simulated value at small bias confirms that the additional capacitance peak originates from the interface states at the SiO2/Si-substrate interface. The discrepancy at large bias is caused by the phonon-assisted tunneling in a large electric field [7], as shown in Fig. 5. Deep-level transient spectroscopy (DLTS) is applied in further investigation of the trapping states in the oxide region. Figure 6 shows the bias-dependent DLTS spectra of the investigated samples ((a) no_dot, (b) small_dot, and (c) dot). All of these samples have an apparent peak (Ei). The dot-sample has an additional peak (Ed) as the bias is swept from 2 to 3 V, as shown in Fig. 6 (c) (indicated by an arrow). According to the bias, emission time, and activation energy, the electric state of the apparent peak (Ei) originates from the interface state, which was analyzed above. Thus, the additional peak (Ed) of the dot-sample originates from the trapping states in the oxide region. Since these trapping states are not observed in the no_dot-sample, they are related to Si-NCs. These trapping states are examined in detail by simulating the band structure. Table 2 shows the activation energy (Ea) and capture cross section (σ) that were obtained from these trapping states by DLTS; the band structure simulation is based on the biases that were applied in this experiment. Figure 7 shows the simulated band structure for (a) VG= -2.24 V (flat-band voltage) and (b) VG= 1.8 V. This simulated band structure reveals that the Fermi level is close to Si-NCs when the trapping states are measured. This result demonstrates that the signal of the trapping states is produced by the Si-NCs. The simulation of the band structure reveals other important mechanisms. At applied biases of 2 V to 3.5 V, the Fermi level is swept through the CB of Si-NCs. This consequence reveals that the Si-NCs form quantum confined states above the CB of Si-NCs, and the trapping states below the CB of Si-NCs are probably the localized states that are produced by the composition fluctuation of Si-NCs. The above results demonstrate that embedded Si-NCs in nitride act as a formation of Si-quantum dots in nitride. Programming carriers is applied to understand the variation of electric properties after “WRITE” operation. Figure 8 shows the DLTS spectra of the dot-sample under three conditions ((a) no-programmed, (b) less-programmed, and (c) programmed). Excluding the voltage shift, the properties (activation energy and capture cross section) of the SiO2/Si-substrate interface states remain almost unchanged, as indicated in Table 3. Therefore, the time constant of the interface states at the SiO2/Si-substrate is fixed to observe the time constant of the Si-quantum dots states. The time constant of the Si-quantum dots states increases during programming carriers, as shown in Fig. 8 (indicated by an arrow), leading to the increase of the activation energy, as indicated in Table 4. Based on DLTS theory [8], the peak of the Si-quantum dots states originates from the hole emission or the electron capture. According to the simulation of the band structure, the peak of the Si-quantum dots states originates from the electron capture, and the time constant corresponds to the capture time of these states. The increase of the activation energy during programming carriers suggests that the electrons cannot easily be transported into Si-quantum dots states after programming carriers, and that the electrons on Si-quantum dots states also cannot easily be transported into the Si-substrate CB. Based on this mechanism, the Si-quantum dots states can be effortlessly programmed (~330 meV), and the electrons on these states after programming can be reserved more easily (~430 meV). Conclusions This study elucidates the fundamental electric properties of SONOS memories with embedded Si-NCs in nitride. Initially, the interface states at the SiO2/Si-substrate are identified by experiment and simulation. Embedded Si-NCs in nitride are confirmed as a formation of Si-quantum dots in nitride. The electron capture time of the Si-quantum dots states is increased during programming carriers. This mechanism suggests that the electrons on these states can be reserved more easily after programming. References [1] J. De Blauwe, IEEE Trans. Nanotechnol., vol. 1, no. 1, pp. 72–77, Mar. 2002. [2] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, in IEDM Tech. Dig., 2003, pp. 609–613. [3] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1392–1398, Aug. 2003. [4] M. C. Liu, T. Y. Chiang, P. Y. Kuo, M. H. Chou, Y. H. Wu, H. C. You, C. H. Cheng, S. H. Liu, W. L. Yang, T. F. Lei, and T. S. Chao, 2008 Semicond. Sci. Technol.23 075033. [5] T. Y. Chiang, T. S. Chao, Y. H. Wu, and W. L. Yang, IEEE Trans. Electron Devices, vol. 29, no. 10, pp. 1148–1151, Oct. 2008. [6] J. L. Autran, F. Seigneur, C. Plossu, and B. Balland, J. Appl. Phys. 74, 3932 (1993). [7] G. Vincent, A. Chantre, and D. Bois, J. Appl. Phys. 50, 5484 (1979). [8] D. V. Lang, J. Appl. Phys. 45, 3023 (1974).

High-Performance Poly-Si TFTs with Novel FinFet-like Channel

For the first time, we demonstrate a high performance TFTs with novel FinFet-like channel structure ( FinFet-like channel TFTs, called FL-TFTs). The FL-TFTs exhibit low threshold voltage VTH~0.5V, good subthreshold swing S.S.~ 240mV/dec. and high ION/IOFF ratio>10 without any hydrogen-related plasma treatments. On the other hand, after Ni-salicidation and hydrogen-related plasma treatments, FL-TFTs exhibit steep subthreshold swing S.S.~ 190 mV/dec. and ION/IOFF even higher than 10. The on-state currents can also be enhanced by Ni-salicidation. Introduction Multiple gate MOSFET architectures such as FinFETs are expected to be utilized beyond the 22nm node due to excellent SCE immunity[1]. From a transistor variation and mismatch perspective, FinFETs are considered particularly suitable for further SRAM scaling, thanks to their improved short channel effects behavior and lower channel doping concentration. Therefore, FinFET is the most promising double-gate transistor architecture [2] to extend scaling over planar device. On the other hand, high-performance low-temperature poly-Si thin film transistors (LTPS-TFTs) are recently developed for the employment of active-matrix liquid crystal displays on a glass substrate and for driving integrated circuits for the application of system-on-panel (SOP) and the three-dimensional (3-D) circuit integration elements such as SRAMs and DRAMs [3]–[5]. Besides, high-speed display driving circuits require thin film transistor (TFTs) to operate at low voltages and high driving currents, with a low threshold voltage. In this work, we demonstrate novel high performance TFTs with FinFETs-like channel by using very simple method. High-performance CFIN-TFTs of a low off leakage current, good S.S., and high ION/IOFF ratio can be obtained, which are very promising for the realization of SOP and 3-D circuit integration. Device Fabrication Process Fig. 1 shows the process flow of the FL-TFTs in this work. First, the dummy layer with 150nm SiN and 150nm TEOS was deposited on the 500nm wet oxide [Fig. 1(a)]. After the dummy pattern was defined, a 50nm a-Si layer was deposited by low-pressure (LPCVD) [Fig. 1(b)]. Next, an annealing step was performed at 600°C in N2 ambient for 24 hrs to transform the a-Si into poly-Si, and dummy spacer was then formed [Fig. 1(b)]. Subsequently, source and drain region was defined, and the FinFet-like channel was formed by the reactive ion etching [Fig. 1(c)]. Then the TEOS dummy layer was removed [Fig. 1(d)]. 15nm chemical vapor deposition (CVD) oxide layer and 300-nm a-Si gate was deposited and patterned by reactive ion etching [Fig. 1(e)]. After the gate-stack formation, source and drain (S/D) regions were implanted with phosphorus, then activated with the TEOS spacer formation simultaneously. Ni-salicidation was achieved by RTA (rapid thermal annealing) at 450C for 30sec. Finally, metallization and sintering were performed to complete the fabrication. Results and Discussion TRANSISTOR PERFORMANCE AND CHARACTERISTICS: Fig.2 shows the scanning electron microscope (SEM) microphotograph of the FL-TFTs. The gate length of FL-TFTs is 0.35m. Fig.3. shows the cross-section transmission electron microscope (TEM) micro-photograph of the FL-TFTs. Fig. 4 shows the ID-VG characteristics of FL-TFTs before any hydrogenrelated plasma treatments and Ni-salicidation process. The FL-TFTs exhibit good swing~240 mV/dec and high ION/IOFF ratio>10. In the Fig. 5, the FL-TFTs used the Ni-salicidation process and underwent the 30 min NH3 plasma treatment, and the Control-TFTs with conventional planer process were also fabricated for comparison. The FL-TFTs shows the better ID-VG characteristics (SS~190 mV/dec. and IOFF~10, ION/IOFF ratio~10 ) than the Control-TFTs (SS~450 mV/dec. and IOFF~10, ION/IOFF ratio>10 ). The better performances of FL-TFTs can be attributed to the good gate control capability owing to the multiple gate structure. On the other hand, the FL-TFTs exhibit better performance after the Ni-salicidation process and the NH3 plasma treatment. The on-state current can be significantly improved by reducing series resistance of S/D with Ni-salicidation and repairing the defect with the NH3 plasma treatment. Fig. 6 shows the field-effect mobility μFE between the FL-TFTs and Control-TFTs. Furthermore, the FL-TFTs devices exhibit extremely high drive currents, as illustrated in Figs. 7. The high driving current would be very suitable for the application of SOP and 3-D circuit integration. TABLE I show device performance comparison between this work and published high performance TFTs data. Conclusions The high performance TFTs (FL-TFTs) with FinFet-like channel film has been proposed. The process is very simple and low cost. The FinFet-like structure can achieve a low off leakage current, good S.S., and high ION/IOFF ratio simultaneously. The high performances of FL-TFTs can be attributed to the good gate control capability by the multiple gate structure. The high performances of FinFet-like structure would be very promising for the application of SOP. References [1] J. Kavalerios., VLSI Symp. Tech. Dig., pp. 50–51, 2006 [2] H.S. P. Wong et. al., IEEE Proceedings, p.537, 1999 [3] Y. Oana et al., J. Soc. Inf. Disp., vol. 9, no. 3, pp. 169–172, 2001. [4] F. Hayashi et al., IEDM Tech. Dig., pp. 283–286, 1996 [5] H. J. Cho et al., VLSI Symp. Tech. Dig., pp. 38–39, 1998 -219Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp219-220 P-1-18

The Compact Modeling of Zero Temperature Coefficient (ZTC) Point of DTMOS

For the first time, the compact analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. Newly analytical formulations are developed for both linear and saturation regions of DTMOS transistor operation that ensure the drain current to be temperature independent for the optimal gate voltage. The maximum error of 0.87% and 2.35% in the linear and saturation regions confirms good agreement between our DTMOS ZTC point model and the experimental data, respectively. Compared to traditional MOSFET, the lower Vg(ZTC) with higher overdrive current of DTMOS improves the speed and efficiency of ICs for the low power consumption requirement in green CMOS technology.

Novel Dynamic Threshold Voltage Contact Etching Stop Layer (DT-CESL) Strained HfO 2 nMOSFET for Very Low Voltage Operation (0.7V)

nMOSFET for Very Low Voltage Operation (0.7V) Woei-Cherng Wu, Tien-Sheng Chao, Kuan-Ti Wang, Shih-Ching Lee, Te-Hsin Chiu, Tsung-Yi Lu, Chao-Sung Lai, Jer-Chyi Wang, Ming-Wen Ma, Kuo-Hsing Kao, and Wen-Cheng Lo Department of Electrophysics, National Chiao Tung University, 1001 Ta Hsueh Rd, Hsinchu, Taiwan Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, Taiwan Department of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh Rd, Hsinchu, Taiwan Tel: +886-3-5131367 Fax: +886-3-5725230 e-mail: tschao@mail.nctu.edu.tw

Novel Field-Induced Gray-Level Selective Patterning of Self-Assembled Aminosilane Monolayer on the SiO 2 Surfaces by using Scanning Probe Bond Breaking Lithography

monolayer on the SiO2 surfaces by using scanning probe bond breaking lithography Chia-Hao Wu , Jeng-Tzong Sheu , Jiun-Shian Jiang , Kuei-Lin Pai , and Tieng-Sheng Chao 3 Institute and Department of Computer Science and Information Engineering, MingDao University 369 Wen-Hwa Road, Peetow, ChangHua 52345, Taiwan Phone: +886-4-8876660-ext.8125 *E-mail: chiahao@mdu.edu.tw 2 Institute of Nanotechnology, National Chiao Tung University Institute and Department of Electrophysics, National Chiao Tung University 1001 Ta Hsueh Road, Hsinchu 30050, Taiwan