Yasutaka Horiba

Three dimensional IC for high performance image signal processor

The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This device gives a clear image of the intelligent image processor on one chip as a future application of 3-D ICs.

A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree

This paper presents an efficient layout method for a high-speed multiplier. The Wallace-tree method is generally used for high-speed multipliers. In the conventional Wallace tree, however, every partial product is added in a single direction from top to bottom. Therefore, the number of adders increases as the adding stage moves forward. As a result, it generates a dead area when the multiplier is laid out in a rectangle. To solve this problem, we propose a rectangular Wallace-tree construction method. In our method, the partial products are divided into two groups and added in the opposite direction. The partial products in the first group are added downward, and the partial products in the second group are added upward. Using this method, we eliminate the dead area. Also, we optimized the carry propagation between the two groups to realize high speed and a simple layout, We applied it to a 54/spl times/54-bit multiplier. The 980 /spl mu/m/spl times/1000 /spl mu/m area size and the 600 MHz clock speed have been achieved using 0.18 /spl mu/m CMOS technology.

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment. >

A bipolar 2500-gate subnanosecond masterslice LSI

A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package.

High pressure oxidation for isolation of high speed bipolar devices

High pressure oxidation has been applied to the oxide isolation of high speed bipolar LSI, with fully ion-implanted shallow junctions and multilevel metallization. A sorter oxidation time for the thick field oxide brought about a smaller redistribution of impurities of a buried collector, which resulted in almost 30 % higher breakdown voltage of devices and also a smaller base-collector capacitance (CTC). A propagation delay time of an ECL gate was improved approximately 10% at low power operation due to the small CTC. A minimum delay time of 0.6 nsec/gate with power consumpation of 1.3 mW(0.8 pJ) was obtained. Oxidation induced defects were greatly influenced with high pressure oxidation temperature, and the optimum temperature was found to be around 1050°C. A master/slice ECL gate array including 900 internal gates was fabricated by utilizing high pressure oxidation technology. The device performance was characterized by the average propagation delay time of 0.9 nsec/gate(1.2 pJ) and chip power consumption of 1.5 watts.

Vertical injection logic

A novel structure, Vertical Injection Logic (VIL) is proposed for getting a superior power-delay product. VIL has a device structure in which PNP transistor is arranged vertically below NPN transistor to obtain the narrow base width by two diffusion steps. The current gain of the PNP device described increases to almost 0.9 in comparison with 0.4 of the usual one. The experimental results show a minimum stage delay of 8.8 ns and a power-delay product of 0.07 pJ compared to 37 ns and 0.3 pJ for the usual I2L device.

A new I 2 L memory cell - Double diffused base structure

A new structure of I2L static memory cell is proposed to improve the electrical characteristics. The cell was fabricated by the double diffused base technology. An additional p-type dopant was introduced to the base region of the bit transistor before the usual base diffusion. The downward current gain of the bit transistor has been successfully reduced by increasing the base width without influencing the upward current gain of the flip-flop transistor. As a result, a minimum write pulse width of 40 ns was obtained compared with 100-200 ns in the conventional structure. A static 1K bits I2L RAM, which was developed by introducing the new structure cell, operated at an address access time of 20 ns and a write pulse width of 40 ns with a power dissipation of 350 mW.

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design

Adaptive voltage management (AVM) scheme is proposed for worst-caseless lower voltage SoC design. The AVM scheme detects the temperature accurately by using two oscillators with different temperature characteristics, and sets supply voltage most suitable with a table look-up method corresponding to the process variation. Also, the AVM can supply the stable voltage with a local shift type regulator even at lower voltage. Thereby, this supply-voltage control system considering PVT variations can control the internal voltage corresponding to process and temperature variations and can realize a wide-operating-margin, DFM function for low voltage SoC. The experimental chip is fabricated on a 90 nm CMOS process, and it was confirmed that the proposed architecture controls the voltage accurately and has a wide operating margin at a lower voltage.

High speed bipolar process with full ion implantation and self-aligned contact structure

Technology for the fabrication of fully ion implanted ECL RAM with arsenic buried collector, boron base and arsenic implanted self-aligned contact (ISAC) emitter is developed combined with dielectric isolation technology, N-type epitaxy and conventional two level metallization. Typical gate delay time tpdis obtained of 0.5 ns with a switching current of 1 mA and 0.9 ns with 0.25 mA from 5-stage ECL ring oscillators. Address access time of 10 ns and a power dissipation of 350 mW are obtained with 1k-bit RAM in ECL version.

Double ion implanted DSAMOS-bipolar devices

The new DSAMOS-bipolar compatible devices have been developed by utilizing the high transcoductance / input impedance of DSA MOS transistor and driving capability of bipolar one for large current. In the double diffused technology, dopants were deposited by the ion implanting method, which resulted in the better threshold voltage controllability (ΔV/Vth=0.05) for DSA MOSFET and high current gain (β=800) for npn transistor. High transconductance of 1.3 mΩ3 was obtained with small size transistor (W =300 µm). The optimum value of base dose was determined by the relationship between Vth and ρsb (base sheet resistance for analogue circuit use.