Takahito Nakazawa

Flip chip underfill reliability of CSP during IR reflow soldering

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less than 10% within wafer. Eutectic solder flip chip assembly process, which includes bonding, cleaning and underfilling, has been also developed. Bonding process of eutectic solder indicates good self-alignment. The excellent rosin cleaning was achieved by the ultrasonic cleaning process with Techno Care. In underfilling process, the underfill resin which can be applied to small stand-off have been chosen. Reliability tests for CSP and flip chip interconnection were carried out and confirmed the good reliability of fabrication process using eutectic solder flip chip technology.