Masayoshi Shirahata

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V/sub th/ lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V/sub th/ lowering at 0.4- mu m gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4- mu m gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4- mu m gate length. >

A mobility model including the screening effect in MOS inversion layer

A mobility model for MOSFET device simulation is proposed. The model is not only applicable to both inversion layer and source/drain high concentration regions of a MOSFET, but it also takes into account the screening effect in the inversion layer. The model also includes an improved normal-field dependence for thin gate oxide MOSFETs. The low parallel electric field mobility is estimated by adding mobilities due to donor scattering, acceptor scattering and lattice scattering using Matthiesens rule. Mobilities due to both the donor and the acceptor scattering include the electron screening effect. The mobility due to lattice scattering is formed as a function of normal electric field E/sub n/, including the strong dependence term of E/sub n/, to express surface roughness scattering. Calculation results of the device simulation using the mobility model show good agreement with the experimental data for various channel dopings. >

The Impact of Nitrogen Implantation into Highly Doped Polysilicon Gates for Highly Reliable and High-Performance Sub-Quarter-Micron Dual-Gate Complementary Metal Oxide Semiconductor

We studied the effects of nitrogen implantation into highly doped polysilicon gates in detail. It was found that highly arsenic-doped polysilicon gates caused degradation of gate oxide films and highly boron-doped polysilicon gates resulted in a shift of threshold voltage by boron penetration. Nitrogen implantation into polysilicon gates can effectively overcome these problems. The nitrogen implanted into the polysilicon gate is segregated into the gate oxide film during heat treatment after implantation. The nitrogen in the gate oxide film can act as a barrier layer for boron penetration and reduce the random failures of gate oxide films under highly doped polysilicon gates. Moreover, the hot carrier resistance can also be improved by nitrogen implantation. Highly reliable and high-performance dual-gate Complementary metal oxide semiconductor (CMOS) can be realized by the highly doped gate and the nitrogen implantation technique.

A Self-Consistent Monte Carlo Simulation for Two-Dimensional Electron Transport in MOS Inversion Layer

Hot electron transport in a MOS inversion layer on a (100) silicon surface was analyzed by using a rigorous Monte Carlo method while taking into account changes in subband structures due to electron repopulation. An iterative procedure of the method consisted of a self-consistent calculation of the Schrodinger and Poissons equations as well as a Monte Carlo calculation for electron scattering. The calculated relative electron population in each subband significantly differed from the results of a conventional Monte Carlo calculation in a tangential electric field higher than 10 kV/cm, above which carrier heating effects greatly influence the subband structures. The calculated electron drift velocity is in reasonable agreement with the experimental data.

Normal Electric Field Dependence of Electron Mobility in MOS Inversion Layer

Short channel MOSFETs with a channel length of 0.38 µm were experimentally investigated and analyzed using a two-dimensional device simulation. FET characteristics can be explained well when the effect of the normal field on the electron mobility (Cooper-Nelson formulas) in the inversion layers is taken into account. The normal field dependence of the electron mobility is interpreted in terms of a two-dimensional quantization of the electrons.

The effects on metal oxide semiconductor field effect transistor properties of nitrogen implantation into p+ polysilicon gate

We have studied in detail the effects of nitrogen implantation into a p+ polysilicon gate on gate oxide properties for the surface p-channel metal oxide semiconductor (PMOS) below 0.25 µm. The nitrided oxide film can be easily formed by the pile-up of nitrogen into the gate oxide film from the polysilicon gate. It was found that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into a p+ polysilicon gate because nitrogen in the polysilicon film can suppress boron diffusion, and the nitrided oxide film can also act as a barrier to boron diffusion. Moreover the hot-carrier hardness can be remarkably improved by the nitrided oxide film since interface state generation can be suppressed by the nitrided oxide film. Furthermore the number of electron traps in the gate oxide film can also be reduced by nitrogen implantation.

Clarification of nitridation effect on oxide formation methods

The electrical characteristics of gate dielectrics have been intensively studied. We examined four types of gate dielectrics: thermal oxide films formed in a pyrogenic steam ambient, those in a dry oxygen ambient, chemical vapor deposition (CVD) oxide films, and the thermal/CVD stacked oxide films. The effects of nitridation on oxide properties have been also systematically investigated using the nitrogen implantation technique. It is found that hot-carrier degradation can be improved by nitridation irrespective of the oxidation methods. This improvement is attributed to the suppression of interface state generation and the reduction in the number of electron traps in the oxide films. Our extensive investigation concludes that the nitridation of gate oxide films by nitrogen implantation is very promising for the improvement in reliability in spite of the difference in oxide formation methods.

Modified Gate Re-Oxidation Technology for High-Performance Embedded Dynamic RAM by Self-Adjusted Gate Bird's Beak

The modified gate re-oxidation is described, which is a very effective simple method of improving the memory retention characteristics of embedded dynamic random access memory (DRAM). This new method forms a gate birds beak through furnace oxidation after the formation of a silicon nitride gate spacer. The amount of gate birds beak formed by this method is self-adjusted according to the gate width of each transistor. Large gate birds beaks are formed selectively for narrow gate transistors. Therefore, gate-induced drain leakage (GIDL) current is suppressed for DRAM cell transistors, without any negative influence on high-speed random logic transistors. The modified gate re-oxidation sample has much better hot carrier reliability than the conventional gate re-oxidation sample. There is almost no difference in the dielectric reliability of gate oxide between the modified sample and the conventional sample. Consequently, this new process realizes the ideal embedded DRAM that has both a highly reliable memory region and a high-speed logic region.

Reliability of source-to-drain non-uniformly doped channel (NUDC) mOSFETs for sub-quarter-micron region

We present an analysis of hot carrier degradation in source-to-drain nonuniformely doped channel (NUDC) metal oxide semiconductor field effect transistors (MOSFETs). Simulation has been performed in order to investigate the influence of the NUDC structure on the device characteristics. It is demonstrated that the hot carrier resistance of NUDC MOSFETs is almost the same as that of conventional MOSFETs when thin gate oxide is used. This is due to the drain electric field strength of NUDC MOSFETs, which becomes the same as that of conventional MOSFETs when the gate oxide is thin, since the drain electric field is not only affected by the channel impurity profile but also strongly influenced by the gate electrode.

Reliability of Non-Uniformly Doped Channel (NUDC) MOSFETs for Sub-Quarter-Micron Region

. This paper prasents the analysis of hot carrier degradation of NLJDC MOSFETs. Simulation has been perfdln€d in oder to inr€stigate the influence of the NUDC stsuctrreon device characteristics. It is demonstrated that allg hot carrbr rcsistance of the_NUDC MOSFETS is quits comparable to hat ofthe conventional MOSFETs for low voltage operarion using ddn gae oxid€, This reason is explained by the drain electric filed strength of the NUDC MOSFETs, which is tlie same as thit of fte conventional MOSFETS due o the thin oxide, sinc€ the drain electric field is not only affected by th€ channel impurity but also stongly influenc€d by the gate el€ctrode.