Yoshinori Okumura

Novel NICE (nitrogen implantation into CMOS gate electrode and source-drain) structure for high reliability and high performance 0.25 /spl mu/m dual gate CMOS

We have proposed a novel structure with high reliability and high performance by nitrogen implantation into gate electrode and source-drain region for 0.25 /spl mu/m dual gate CMOS. It was found that the hot carrier resistance of both N-ch and P-ch MOSFETs can be effectively improved by incorporating nitrogen into the gate oxide with nitrogen implantation on the poly silicon gate. Moreover it was found that Ti-salicided shallow junction for 0.25 /spl mu/m CMOS can be successfully formed without increasing the junction leakage current.<<ETX>>

The effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties

We have studied the effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties in detail for the surface channel PMOS below 0.25 /spl mu/m. It was founded that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into P/sup +/ poly-silicon gate. Moreover the generation of interface states and traps can be also reduced by nitrogen implantation. Therefore the resistance against the hot carrier injection can be dramatically improved. These improvements would be due to the incorporation of nitrogen into gate oxide film and the reduction of boron and fluorine atoms in the gate oxide film.<<ETX>>

A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET for high current drivability and threshold voltage controllability

A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET was investigated theoretically and experimentally. Using an analytical model, it is verified that the mobility of the NUDC MOSFET is increased as compared with that of the conventional channel MOSFET. Also, the V/sub th/ lowering of the NUDC MOSFET is suppressed as compared with that of the conventional channel MOSFET. The NUDC MOSFET was fabricated by the oblique rotating ion implantation technique, and the theoretical predictions were confirmed experimentally.<<ETX>>

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

We propose an advanced sub-quarter micron CMOS process for ultra shallow junctions and high reliability using a new nitrogen implantation technique. Nitrogen atoms implanted into the source/drain for NMOSFETs and PMOSFETs can suppress impurity diffusion and leakage current, since not only can nitrogen atoms occupy the diffusion path of arsenic and boron atoms but also the secondary defects induced by nitrogen implantation can act as a surface proximity gettering site. Moreover, this technique can remarkably suppress the hot carrier degradation for CMOS LDD FETs, since the segregation of nitrogen at interface between the substrate and the side-wall SiO/sub 2/ can reduce the interface state generation under the side-wall spacer.

A novel stacked capacitor cell with dual cell plate for 64 Mb DRAMs

The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capacitance of this cell increases significantly compared to the conventional stacked capacitor cell. For a 1.3- mu m/sup 2/ cell, the DCP cell should achieve a storage capacitance of more than 25 fF. The experimental results indicate that the DCP cell can realize the 64-Mb DRAMs and 1.3- mu m/sup 2/ cell area using the 0.3- mu m design rule.<<ETX>>

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current. >

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

A 0.25 /spl mu/m W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by a non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation

An advanced nitrogen implantation technique is proposed. The new technique can suppress remarkably the hot carrier degradation. Since the generation of interface states can be reduced by the incorporation of nitrogen at the interface between a substrate and SiO/sub 2/ spacers. Moreover, the ultra shallow junction without the increase in leakage current can be formed by nitrogen implantation into the source/drain. Since the secondary defects induced by nitrogen implantation can act as a surface proximity gettering (SPG) site.

Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm

The high performance 0.25 /spl mu/m dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with an Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore, the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot-hole injection.

Novel low offset voltage diode using asymmetric threshold voltage MONOS-FET for next generation devices demanding low voltage operation

Novel diode with low offset voltage below 0.6V is proposed by using MONOS FET with asymmetric threshold voltage. Offset voltage of 0.3V can be achieved by suppressing off state current and reverse leakage current. This technique gives promising characteristics for next generation circuits with low voltage operation.