Takayuki Hamada

Split capacitor DAC mismatch calibration in successive approximation ADC

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply.

A dynamic offset control technique for comparator design in scaled CMOS technology

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

Jump phenomenon by feedback control of flyback converter

Applying feedback control to a flyback converter in discontinuous conduction mode causes instability by a jump phenomenon under some snubber circuit conditions. In this paper, we clarify this jump phenomenon, analyze stability, and discuss circuit constants to avoid this jump phenomenon. We propose current-mode control without relying on circuit constants.