Takumi Ota

Maskless lithography: a low-energy electron-beam direct writing system with a common CP aperture and the recent progress

In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.

What is the strongest candidate in lithography for 2x nm HP and beyond

We have investigated three candidate lithography technologies for 2x nm HP generation and beyond for the application to LSI, namely, double patterning technology (DPT), EUV lithography (EUVL) and nanoimprint lithography (NIL). In terms of lithography unit technologies and lithography integration technologies, each technology has advantages and disadvantages from the viewpoint of difficulty, development resources, extendability, process cost, and so on. Using a development matrix consisting of development steps and development stages, we clarified the current development status for each technology. This matrix indicates the items for which technological critical breakthroughs are necessary to realize LSI production. From this study, we made three lithography development scenarios for the feasibility stage and the production stage for 2x nm HP generation and beyond.

A study of voltage contrast image using Monte Carlo simulation

Using Monte Carlo simulation, we studied voltage contrast (VC) image caused by negative charging. In order to simulate the VC image, we have developed an electron scattering program based on a consideration of the spatial charge conduction model. Also we have established a cluster computing system of 60 CPUs to shorten the processing time. Using a Monte Carlo simulator, we succeeded in obtaining the simulated VC image. Comparison between simulated images and experimental images reveals that the simulated images are in good agreement with some experimental images.

Exposure characteristics of character projection-type low-energy electron-beam direct writing system

We have developed a character projection (CP)-type low-energy electron beam (EB) direct writing (EBDW) system called EBIS (Electron Beam Integrated System). A low-energy EB of less than 5 keV has the potential to expose by the CP-method without intra- and inter-layer proximity effect corrections. In this paper, the advantages of the proximity effect of the low-energy EBDW system of 5 keV with the CP exposure are discussed. The experimental results to compare the intra-layer proximity effect between 5 keV and 50 keV showed that the low-energy EB has an advantage over high-energy EB in terms of small shot size deviation at the pattern edge. The experimental results of inter-layer proximity effect of 5 keV indicate that no proximity effect corrections for structures in underlying layers are necessary in the case of the combination of low-energy EB and multi-layer resist. On the other hand, in response to concern about the Coulomb interaction effect, which is a critical problem of low-energy EB, a dose correction function of each shot was proposed for the EBIS system. We are convinced that the low-energy EBDW is useful for exposure of practical patterns of logic devices by the CP exposure with higher throughput, because the proximity effect is so small that complicated corrections due to the adjacent pattern and structures of substrate under exposure layer are unnecessary.