Tatsuhiko Higashiki

Nanoimprint lithography and future patterning for semiconductor devices

Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed.

Nanoimprint Lithography for Semiconductor Devices and Future Patterning Innovation

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

Aberration budget in extreme ultraviolet lithography

It seems that the actual EUV lithography tools will have aberrations around ten times larger than those of the latest ArF lithography tools in wavelength normalized rms. We calculated the influence of aberrations on the size error and pattern shift error using Zernike sensitivity analysis. Mask-induced aberration restricts the specification of aberration. Without periodic additional pattern, the aberration to form 22 nm dual-gate patterns was below 8 mλ rms. Arranging the periodic additional pattern relaxed the aberration tolerance. With periodic additional pattern, the aberration to form 22 nm patterns was below 37 mλ rms. It is important to make pattern periodicity for the relaxation of the aberration specification.

Development of a Platform for Collaborative Engineering Data Flow between Design and Manufacturing

The amount of collaborative engineering data between design and manufacturing is increasing because of the introduction of design for manufacturing (DFM) technology to improve product yield quickly. Therefore, we developed a platform to realize collaborative engineering data flows between design and manufacturing. The platform can facilitate the implementation of flows of yield ramp-up and quick turn-around-time (TAT). The flows can reduce the TA T of information linkage. The flows which improve yield and manufacturability were established on the platform and integrated into the actual LSI production. As a result, we confirmed the improvement of efficiency of the system development and the TAT reduction of information linkage.

Alignment mark signal simulation system for the optimum mark feature selection

Recently, requirements concerning overlay accuracy have become much more restrictive. For the accurate overlay, signal intensity and wave form from the topographical alignment mark have been examined by signal simulation. However, even if the results were in good agreement with actual signal profiles, it would be difficult to select particular alignment marks at each mask level by the signal simulation. Therefore, many mark candidates are left in the kerf area after mass production. To facilitate the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation performed in advance. In our system, the alignment mark signal can be easily simulated after input of some process material parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. Imaging of the reflected beams through inspection optics is simulated. In addition, we show two applications. This system is not only for predicting and showing a signal wave form, but is also helpful for finding the optimum marks.

Integration of a new alignment sensor for advanced technology nodes

In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensors infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

Basic studies of overlay performance on immersion lithography tool

Immersion lithography with ArF light and Ultra Pure Water (UPW) is the most promising technology for semiconductor manufacturing with 65 nm hp design and below. Since Nikon completed the first full-field immersion scanner, the Engineering Evaluation Tool (EET, NA=0.85) at the end of 2004, Toshiba and Nikon have investigated overlay accuracy with the EET which uses the local fill nozzle. EET successfully demonstrated immersion tools are comparable in single machine overlay accuracy to dry tools, and immersion-dry matching has the same level overlay matching accuracy as dry-dry matching. EET also made it clear that overlay accuracy is independent of scanning speed, and both solvent-soluble topcoats, as well as developer-soluble topcoats can be used without degradation of overlay accuracy. We investigated the impact of the thermal environment on overlay accuracy also, assuming that a key technology of overlay with immersion tools must achieve thermal stabilities similar to dry tools. It was found that the temperature of supply water and loading wafer are stable enough to keep the overlay accuracy good. As for evaporation heat, water droplets on the backside of the wafer lead to overlay degradation. We have decided to equip the wafer holder of S609B, the first immersion production model, with an advanced watertight structure.

Design for manufacture to deal with mask-induced critical dimension errors in the extreme ultraviolet

Abstract. The actual extreme ultraviolet lithography tools will have ab-errations around seven times larger than those of the latest ArF lithogra-phy tools in wavelength normalized rms. We calculated the influence ofaberrations on the size error and pattern shift error using Zernike sensi-tivity analysis. Mask-induced aberration restricts the specification of ab-erration. Without periodic additional pattern, the aberration level that canbe accepted to form 22 nm dual-gate patterns was 8m rms. Arrang-ing the periodic additional pattern relaxed the aberration tolerance. Withperiodic additional pattern, the acceptable aberration level to form 22 nmpatterns was below 37 m rms. It is important to make pattern period-icity for the relaxation of the aberration specification.

What is the strongest candidate in lithography for 2x nm HP and beyond

We have investigated three candidate lithography technologies for 2x nm HP generation and beyond for the application to LSI, namely, double patterning technology (DPT), EUV lithography (EUVL) and nanoimprint lithography (NIL). In terms of lithography unit technologies and lithography integration technologies, each technology has advantages and disadvantages from the viewpoint of difficulty, development resources, extendability, process cost, and so on. Using a development matrix consisting of development steps and development stages, we clarified the current development status for each technology. This matrix indicates the items for which technological critical breakthroughs are necessary to realize LSI production. From this study, we made three lithography development scenarios for the feasibility stage and the production stage for 2x nm HP generation and beyond.

Flexible alignment mark design applications using a next generation phase grating alignment system

In this paper, alignment and overlay results on processed short-flow wafers are presented. The impact of various mark designs on overlay performance was investigated, using a newly developed phase grating wafer alignment sensor concept. This concept is especially suited to support mark design flexibility, as well as to further improve upon the performance of the alignment sensors currently known. The unique sensor concept allows for alignment to a large variety of marks layouts, thereby complying with customer specific alignment mark design requirements. Here, we present alignment performance results on Toshibas new marks. For this purpose, the new alignment sensor was integrated in an ASML proto-type tool. Alignment performance on ASML default mark types was demonstrated to guarantee backward compatibility with known alignment sensors. Alignment repeatability numbers of <3 nm (3sigma) were obtained for the different mark designs investigated. These numbers were measured on marks in resist as well as on processed short flow lots. Short term overlay capability of <6 nm (mean+3sigma) was demonstrated on Toshiba mark types, and on ASML mark types. Long term overlay values were demonstrated to be below 8 nm (mean + 3sigma) for both mark designs. The alignment and overlay capability, on processed wafers, was demonstrated for two process modules: Gate-to-Active (GC-AA) and Metal1-to-Contact (M1-CS). Typical overlay values measured were 20 to 30 nm, for the GC-AA and the M1-CS process module respectively. Further improvements with respect to alignment performance and overlay capability are anticipated through the use of advanced applications, and by further optimization of alignment mark design. This will be verified in future joint Toshiba/ASML experiments.