Tatsuya Kunikiyo

Effect of channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length

A high performance CMOSFET with a channel along the <100> crystallographic axis has been developed. Current drivability of the pMOSFET is improved by about 15% by changing the channel direction from <110> to <100> due to an increase in hole mobility and high immunity against short channel effects (SCE). As a result, a drive current of 810 /spl mu/A//spl mu/m for nMOS and of 420 /spl mu/A//spl mu/m for pMOS with 0.14 /spl mu/m gate length has been achieved under 1 nA//spl mu/m off current at 1.8 V operation.

Three-dimensional topography simulation model: etching and lithography

An etching model in which topography is derived by solving a modified diffusion equation is introduced. This model is simple and makes it possible to simulate three-dimensional (3-D) topography accurately and quickly. Based on this model, a 3-D topography simulator which can be applied in the development of photolithography and isotropic/anisotropic etching has been developed. With this simulator, it is possible to simulate the series processes and multilayer etching, such as contact hole and trench etching. By simulating photolithography, diffraction and standing-wave effects can be found clearly in the 3-D topography of the developed photoresist. In the case of an etching process which is restricted by diffusion, the dependence of the etch front topography on the window width of the mask is examined. >

Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation

Presents a physical model of reverse short-channel effects on threshold voltage caused by lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by ion implantation in source/drain region of n-channel MOS devices. Based on the process and device simulation, it is shown that lateral diffusion of the Frenkel pairs enhances diffusion of channel dopant, and results in nonuniform lateral distribution. This phenomenon causes the threshold voltage increase in the short-channel devices. The authors extracted parameters on point-defect diffusion from the comparison of calculated results with experimental data on threshold voltage. Calculated arsenic profile in the source/drain region using those parameters shows good agreement with the experimental data measured by secondary ion mass spectroscopy (SIMS). The close agreement between simulation and experimental results both on the arsenic profile in source/drain region and threshold voltage confirms the validity of the model and extracted parameters. >

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current. >

3-D numerical modeling of thermal flow for insulating thin film using surface diffusion

This paper presents a three-dimensional (3-D) numerical surface diffusion model of BPSG glass flow of surface tension. The analysis region is divided into small cubic cells. Material surface is described as an equi-concentration (equi-existence rate) area which is obtained by linear interpolation between the cells. 3-D surface curvature is defined as the ratio of the increment of surface area to that of volume in a small interface area. Flux of flow is proportional to gradient of the surface curvature, and the direction is from positions of larger curvature to that of small curvature. The flow algorithm is that particles move from the mass-center of the equi-concentration area of a cell to that of the neighbor cells across the contact lines of the cell boundary and the equi-concentration area. This paper presents two 3-D simulations of flow which show that this model can be applied for not only cylindrical symmetry but also general 3-D topography. Also, the surface diffusion coefficient for the total concentration (C/sub imp/: P/sub 2/O/sub 5/ and B/sub 2/O/sub 3/) is derived using the model by fitting 2-D simulations to the experiments at 850/spl deg/C. >

New topography expression model and 3D topography simulation of Al sputter deposition, etching, and photolithography

It is shown that the material surface can be described by the constant concentration area (the contour surface), by using the continuity principle at the material surface and considering the essential property of the material surface. Based on this model and the conservation of mass, the authors present a simulation algorithm and develop a 3D topography simulator (3D MULSS: Three-Dimensional Multi Layer Shape Simulator). It is demonstrated that this simulator can simulate the coverage of Al sputter deposition accurately, by comparing simulations and experimental results. 3D MULSS can also simulate the sequential processes of deposition, etching, and photolithography in three dimensions. In addition, it is shown that the proposed model can be applied to the surface tension by the 2D simulation of reflow.<<ETX>>

Simulation of Dopant Redistribution During Gate Oxidation Including Transient-Enhanced Diffusion Caused by Implantation Damage

Dopant redistribution during gate oxidation in metal-oxide-semiconductor (MOS) fabrication processes has been studied by secondary-ion mass spectrometry (SIMS). In the first set of experiments, dopant profiles after gate oxidation are measured and compared to those after N2 annealing. From the measured profiles, the contribution of oxidation-enhanced diffusion (OED) to the entire dopant redistribution is determined and an OED model parameter is calibrated. In the second set of experiments, samples which are subjected only to wafer loading and unloading steps are prepared and dopant profiles are measured. From the measured profiles, the magnitude of transient-enhanced diffusion (TED) which occurs during the wafer loading step is estimated and an interstitial-clustering parameter is calibrated. The parameters calibrated in this study are combined with the point-defect parameters taken from the literature, and dopant redistribution during the entire gate oxidation cycle is simulated. Calculated dopant profiles agree well with the measured SIMS profiles and show correct time dependence of TED and OED, as observed in the present experiments. In the simulations, interstitial concentration at the oxidizing Si/SiO2 interface is found to be 40 times the equilibrium concentration. The supersaturation caused by surface oxidation is small and the contribution of OED is negligible under typical gate oxidation conditions where oxide thickness is less than 100 A. Dopant profiles after gate oxidation are mainly dominated by TED. However, as oxidation proceeds, the contribution of OED increases because it continues while TED almost ends in the wafer loading step of gate oxidation. Segregation of boron in the channel region is also studied. It is found that a greater amount of boron is lost in oxidation than in N2 annealing. The effect of segregation on device characteristics is not negligible for buried-channel PMOS devices, because the threshold voltage of the devices is sensitive to the change in the amount of boron.