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Dive into the research topics where Masato Fujinaga is active.

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Featured researches published by Masato Fujinaga.


IEEE Transactions on Electron Devices | 1990

Three-dimensional topography simulation model: etching and lithography

Masato Fujinaga; Norihiko Kotani; Tatsuya Kunikiyo; Hidekazu Oda; Masayoshi Shirahata; Y. Akasaka

An etching model in which topography is derived by solving a modified diffusion equation is introduced. This model is simple and makes it possible to simulate three-dimensional (3-D) topography accurately and quickly. Based on this model, a 3-D topography simulator which can be applied in the development of photolithography and isotropic/anisotropic etching has been developed. With this simulator, it is possible to simulate the series processes and multilayer etching, such as contact hole and trench etching. By simulating photolithography, diffraction and standing-wave effects can be found clearly in the 3-D topography of the developed photoresist. In the case of an etching process which is restricted by diffusion, the dependence of the etch front topography on the window width of the mask is examined. >


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994

Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation

Tatsuya Kunikiyo; Katsuyoshi Mitsui; Masato Fujinaga; T. Uchida; Norihiko Kotani

Presents a physical model of reverse short-channel effects on threshold voltage caused by lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by ion implantation in source/drain region of n-channel MOS devices. Based on the process and device simulation, it is shown that lateral diffusion of the Frenkel pairs enhances diffusion of channel dopant, and results in nonuniform lateral distribution. This phenomenon causes the threshold voltage increase in the short-channel devices. The authors extracted parameters on point-defect diffusion from the comparison of calculated results with experimental data on threshold voltage. Calculated arsenic profile in the source/drain region using those parameters shows good agreement with the experimental data measured by secondary ion mass spectroscopy (SIMS). The close agreement between simulation and experimental results both on the arsenic profile in source/drain region and threshold voltage confirms the validity of the model and extracted parameters. >


IEEE Transactions on Electron Devices | 1997

3-D topography simulator (3-D MULSS) based on a physical description of material topography

Masato Fujinaga; Norihiko Kotani

This paper presents a three-dimensional (3-D) topography simulator (3-D MULSS), and its applications. We focus on the description of the material surface and the algorithm of the surface advancement. Then we propose a 3-D topography simulation algorithm, with consideration of the probe size of observation, and based on the integration formula of the balance equation. Next, we show the simulation results of the 3-D MULSS: (1) isotropic deposition; (2) Aluminum-sputter deposition; (3) isotropic etching; (4) anisotropic etching; and (5) sequential process steps. These results make the accuracy of the 3-D MULSS clear, and also show that it is possible to stably simulate the sequential process steps.


Japanese Journal of Applied Physics | 1996

Stable Solution Method for Viscoelastic Oxidation Including Stress-Dependent Viscosity

Tetsuya Uchida; Masato Fujinaga; Norihiko Kotani; Satoru Kawazu; Hirokazu Miyoshi

A new computer program that simulates viscoelastic oxidation of silicon has been developed. Since in this program a tangential procedure is used for time stepping, numerical stability has been improved, and the instability problem that arises from the incorporation of stress dependence into oxide viscosity has been resolved. Thus, oxidation-induced stresses calculated by our program using stress-dependent viscosity have reasonable magnitude over the entire device area. Moreover, in our program, volume expansion due to oxidation of silicon was treated as a dilational strain, as opposed to its treatment as a forced displacement of oxide/silicon interface or a uniaxial strain perpendicular to the interface in most previous programs. Due to this difference, our program can simulate the generation of intrinsic stress below viscous flow temperature (ca. 960°C), and as a result, stress distribution calculated by our program changes drastically at the viscous flow temperature.


NUPAD IV. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, | 1992

Reverse Short-Channel Effects due to the Lateral Diffusion of the Point-Defects Induced by the Source/Drain Ion Implantation

T. Kunikiyo; Katsuyoshi Mitsui; Masato Fujinaga; Tetsuya Uchida; Norihiko Kotani; Yoichi Akasaka

A physical model of reverse short-channel effect on the threshold voltage caused by the lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by tlie ion implantation in the source/drain region is presented. Based on the process and device simulation, it is shown that the lateral diffusion of the Frenkel pairs enhances the diffusion of the channel dopant, which results in the nonuniform lateral distribution of the channel dopant and in the increase in the threshold voltage as the channel length is reduced.


Japanese Journal of Applied Physics | 2015

Switching characteristics of a 4H-SiC insulated-gate bipolar transistor with interface defects up to the nonquasi-static regime

Iliya Pesic; Dondee Navarro; Masato Fujinaga; Yoshiharu Furui; Mitiko Miura-Mattausch

The switching characteristics of a trench-type 4H-SiC insulated-gate bipolar transistor (IGBT) device with interface defects are analyzed up to the nonquasi-static (NQS) switching regime using reported interface density measurements and device simulation. Collector current degradation characterized by threshold voltage shift to higher gate voltages and reduction of current magnitude due to carrier trapping are observed under quasi-static (QS) simulation condition. At slow switching of the gate voltage, carrier trapping causes a hump in the transient current at the start of conduction. At very fast switching, the current hump is limited by the NQS effect which results to a reduced switching efficiency and increased on-resistance.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1995

3-D numerical modeling of thermal flow for insulating thin film using surface diffusion

Masato Fujinaga; I. Tottori; Tatsuya Kunikiyo; T. Uchida; Norihiko Kotani; K. Tsukamoto

This paper presents a three-dimensional (3-D) numerical surface diffusion model of BPSG glass flow of surface tension. The analysis region is divided into small cubic cells. Material surface is described as an equi-concentration (equi-existence rate) area which is obtained by linear interpolation between the cells. 3-D surface curvature is defined as the ratio of the increment of surface area to that of volume in a small interface area. Flux of flow is proportional to gradient of the surface curvature, and the direction is from positions of larger curvature to that of small curvature. The flow algorithm is that particles move from the mass-center of the equi-concentration area of a cell to that of the neighbor cells across the contact lines of the cell boundary and the equi-concentration area. This paper presents two 3-D simulations of flow which show that this model can be applied for not only cylindrical symmetry but also general 3-D topography. Also, the surface diffusion coefficient for the total concentration (C/sub imp/: P/sub 2/O/sub 5/ and B/sub 2/O/sub 3/) is derived using the model by fitting 2-D simulations to the experiments at 850/spl deg/C. >


international electron devices meeting | 1990

New topography expression model and 3D topography simulation of Al sputter deposition, etching, and photolithography

Masato Fujinaga; Tatsuya Kunikiyo; T. Uchida; Norihiko Kotani; A. Osaki; Y. Akasaka

It is shown that the material surface can be described by the constant concentration area (the contour surface), by using the continuity principle at the material surface and considering the essential property of the material surface. Based on this model and the conservation of mass, the authors present a simulation algorithm and develop a 3D topography simulator (3D MULSS: Three-Dimensional Multi Layer Shape Simulator). It is demonstrated that this simulator can simulate the coverage of Al sputter deposition accurately, by comparing simulations and experimental results. 3D MULSS can also simulate the sequential processes of deposition, etching, and photolithography in three dimensions. In addition, it is shown that the proposed model can be applied to the surface tension by the 2D simulation of reflow.<<ETX>>


international electron devices meeting | 1988

Three dimensional topography simulation model using diffusion equation

Masato Fujinaga; Norihiko Kotani; Hidekazu Oda; Masayoshi Shirahata; H. Genjo; T. Katayama; T. Ogawa; Y. Akasaka

An etching model for three-dimensional topography simulation is proposed in which the topography is deduced by solving the diffusion equation. A 3-D topography simulator called 3-D MULSS (multilayer shape simulator) has been developed on the basis of this model. Using this program, contact hole and trench etching was simulated exactly, and the computation was extremely fast.<<ETX>>


Japanese Journal of Applied Physics | 2000

Simulation of Dopant Redistribution During Gate Oxidation Including Transient-Enhanced Diffusion Caused by Implantation Damage

Tetsuya Uchida; Katsumi Eikyu; Eiji Tsukuda; Masato Fujinaga; Akinobu Teramoto; Tomohiro Yamashita; Tatsuya Kunikiyo; Kiyoshi Ishikawa; Norihiko Kotani; Satoru Kawazu; Chihiro Hamaguchi; Tadashi Nishimura

Dopant redistribution during gate oxidation in metal-oxide-semiconductor (MOS) fabrication processes has been studied by secondary-ion mass spectrometry (SIMS). In the first set of experiments, dopant profiles after gate oxidation are measured and compared to those after N2 annealing. From the measured profiles, the contribution of oxidation-enhanced diffusion (OED) to the entire dopant redistribution is determined and an OED model parameter is calibrated. In the second set of experiments, samples which are subjected only to wafer loading and unloading steps are prepared and dopant profiles are measured. From the measured profiles, the magnitude of transient-enhanced diffusion (TED) which occurs during the wafer loading step is estimated and an interstitial-clustering parameter is calibrated. The parameters calibrated in this study are combined with the point-defect parameters taken from the literature, and dopant redistribution during the entire gate oxidation cycle is simulated. Calculated dopant profiles agree well with the measured SIMS profiles and show correct time dependence of TED and OED, as observed in the present experiments. In the simulations, interstitial concentration at the oxidizing Si/SiO2 interface is found to be 40 times the equilibrium concentration. The supersaturation caused by surface oxidation is small and the contribution of OED is negligible under typical gate oxidation conditions where oxide thickness is less than 100 A. Dopant profiles after gate oxidation are mainly dominated by TED. However, as oxidation proceeds, the contribution of OED increases because it continues while TED almost ends in the wafer loading step of gate oxidation. Segregation of boron in the channel region is also studied. It is found that a greater amount of boron is lost in oxidation than in N2 annealing. The effect of segregation on device characteristics is not negligible for buried-channel PMOS devices, because the threshold voltage of the devices is sensitive to the change in the amount of boron.

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Tetsuya Uchida

Tokyo University of Agriculture and Technology

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