Christoph Flötgen

Monolithic Two-Terminal III–V//Si Triple-Junction Solar Cells With 30.2% Efficiency Under 1-Sun AM1.5g

Stacking III-V p-n junctions on top of wafer-based silicon solar cells is a promising way to go beyond the silicon single-junction efficiency limit. In this study, triple-junction GaInP/AlxGa1-xAs//Si solar cells were fabricated using surface-activated direct wafer bonding. Metal-organic-vapor-phase-epitaxy-grown GaInP/AlxGa1-xAs top cells are bonded at low temperature to independently prepared wafer-based silicon cells. n-Si//n-GaAs interfaces were investigated and achieved bulk-like bond strength, high transparency, and conductivity homogeneously over 4-inch wafer area. We used transfer-matrix optical modeling to identify the best design options to reach current-matched two-terminal devices with different mid-cell bandgaps (1.42, 1.47, and 1.52 eV). Solar cells were fabricated accordingly and calibrated under AM1.5g 1-sun conditions. An improved Si back-side passivation process is presented, leading to a current density of 12.4 mA/cm2 (AM1.5g), measured for a flat Si cell below GaAs. The best 4 cm2 GaInP/GaAs//Si triple-junction cell reaches 30.2% 1-sun efficiency.

Cu-Sn transient liquid phase wafer bonding for MEMS applications

The impact of process parameters on final bonding layer quality was investigated for Transient Liquid Phase (TLP) wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in Inter-Metallic Compound (IMC) growth for the mentioned process and design parameters were identified and subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results.

Wafer bonding for vacuum encapsulated MEMS

The working principle of various categories of MEMS devices require inside the packages the encapsulation of vacuum ambient which impacts on device performance. The factors impacting on process choice will be reviewed. Main wafer bonding processes used for such applications will be introduced.

Wafer bonding for CMOS integration and packaging

The use of CMOS wafers imposes important limitations for W2W (Wafer-to-Wafer) or C2W (Chip-to-Wafer) bonding: low processing temperature (max. 400°C), no mobile ions and extreme cleanliness. Additional to substrates preparation a special focus is directed on cleaning and maintaining the wafers clean during processing. Special cleaning processes were adopted for CMOS-compatible applications. The main challenges raised by CMOS-compatible wafer bonding in terms of processing and process control were identified and process solutions will be presented illustrated with examples.

CMOS-compatible aligned fusion wafer bonding

Wafer bonding is a very attractive technology for applications in wafer-level 3D integration. However, most of the bonding processes are not compatible with CMOS technology in terms of process temperature and contamination levels. A low temperature fusion bonding process is presented as an example of how the wafer bonding issues were successfully solved and applied to manufacturing processes.

Room temperature fabrication of semiconductor interfaces

A new technology was developed allowing for room temperature covalent bonding. The surface preparation method allows for in situ native oxides removal and fabrication of oxide-free bonded interfaces which could be directly used in fabrication of various devices (e.g. solar cells).

Metal wafer bonding for 3D interconnects and advanced packaging

Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in manufacturing processes.