Michel J. Abou-Khalil

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas, for 1.0V thin oxide devices, gate-oxide breakdown failure occurred

Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies

Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

Power handling capability of an SOI RF switch

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI

We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by ∼50% with respect to a design where ED is not located under the contacts.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.