Toshiyuki Enda

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET

Mesh related problems in device simulation:: Treatments of meshing noise and leakage current

Abstract Technology CAD (TCAD) becomes more important, because of an increase in a complexity of VLSI design. However, TCAD still requires further improvements from the practical point of view. This paper describes new mesh related problems in a device simulation; a meshing noise and a leakage current problems.

Verification of saturation velocity lowering in MOSFET's inversion layer

With reduction of the MOSFETs channel length L, the drain saturation current of MOSFETs is determined by the saturation velocity v/sub sat/ in the inversion layer. Hence, the modeling of v/sub sat/ becomes very important. In this paper, v/sub sat/ in the inversion layer has been examined by using simulation experiment. New parameter values for v/sub sat/ model in the inversion layer are proposed. In order to verify the v/sub sat/ model, the impurity profiles of MOSFETs are calibrated to fit the threshold voltage V/sub th/-L characteristics. Then, we validate new v/sub sat/ model by comparing the experiments of I/sub D/-V/sub D/ characteristics of 0.35-/spl mu/m CMOS with the simulations using the energy transport model (ETM).

Modeling of Electron Mobility Degradation for HfSiON MISFETs

The electron mobility degradation for HfSiON MISFETs was investigated. We found that the degradation had two origins; one is Coulomb scattering caused by fixed charges in HfSiON films and the other is phonon scattering by interfacial thin oxynitrided (SiON) layer; and HfSiO-related remote phonon scattering is not dominant. The mobility degradation caused by the Coulomb scattering and SiON phonon scattering is separated into two components and we develop an empirical mobility model for HfSiON devices that enables accurate simulation of electrical characteristics of the HfSiON devices

Grid size independent model of inversion layer carrier mobility

The universality of effective carrier mobility in MOSFET inversion layers has been reported. In order to realize the accurate device simulation of MOSFETs, a mobility model considering the universality is indispensable. A local field model (LFM) has been proposed. The LFM proposed was derived from the requirement that the calculated conductance of a whole inversion layer gave the measured value. However, the resulting conductance varies with the grid size strongly. The authors intend to solve this inconsistency, to examine this grid size dependency and propose a new grid size independent LFM.

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

To reduce the short-channel effect for memory cell transistors beyond 2× nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S-factor of 309 mV/decade, wide enough threshold voltage (Vth) window of 15 V between program and erase state, and fast enough program and erase time of 100 µs and 100 µs. And we observed no significant Vth-window narrowing and increase in Vth of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2× nm size NAND EEPROM.

Modeling of NBTI Degradation for SiON pMOSFET

For SiO2 pMOSFETs, the reaction diffusion model is well used to describe the NBTI degradation theoretically and the Ogawa model for hole trap generation is known exper imentally. However, there is not a good model of NBTI degradation for SiON devices. In this paper, we propose a nitrogen dependent hole trap generation model by extending these two models and present the NBTI degradation model for SiON pMOSFETs.

Counter-Doped Surface Channel Metal-Oxide-Semiconductor Field-Effect Transistor with High Current Drivability and Steep Subthreshold Slope

A metal-oxide-semiconductor field-effect transistor (MOSFET) with a novel channel structure called a counter-doped surface channel (CDSC) is proposed. A unique characteristic of the CDSC MOSFET is that the channel current still exists at the surface, even though the counter-doped layer is formed. Experimental results confirm that the CDSC pMOSFET using an n+ poly-Si gate has the highest current drivability and the steepest subthreshold slope while maintaining a good short-channel-effect immunity compared with the surface channel (SC) and buried channel (BC) pMOSFET. The delay time with the CDSC pMOSFET represents 1.34-fold improvement in comparison to that with the SC pMOSFET.