Kazuya Matsuzawa

A unified simulation of Schottky and ohmic contacts

The Schottky contact is an important consideration in the development of semiconductor devices. This paper shows that a practical Schottky contact model is available for a unified device simulation of Schottky and ohmic contacts. The present model includes the thermionic emission at the metal/semiconductor interface and the spatially distributed tunneling calculated at each semiconductor around the interface. Simulation results of rectifying characteristics of Schottky barrier diodes (SBDs) and resistances under high impurity concentration conditions are reasonable, compared with measurements. As examples of application to actual devices, the influence of the contact resistance on salicided MOSFETs with source/drain extension and the immunity of Schottky barrier tunnel transistors (SBTTs) from the short-channel effect (SCE) are demonstrated.

Technology trends of silicon-on-insulator-its advantages and problems to be solved

Recent progress in SOI technology is reviewed and problems which need be solved are discussed. Emphasis is placed on the substrate floating effect, for which the bandgap engineering method is proposed for the first time. It is demonstrated that Si-Ge formation in the source region can improve the drain breakdown voltage significantly.<<ETX>>

Role of long-range and short-range Coulomb potentials in threshold characteristics under discrete dopants in sub-0.1 /spl mu/m Si-MOSFETs

We investigate the Coulomb potential associated with discrete dopants in sub-0.1 /spl mu/m Si-MOSFETs from the physical viewpoint. It is found that the discrimination of the Coulomb potential between the long-range and short-range parts is essential in correctly simulating the device characteristics under nonuniform discrete dopants. A new dopant model appropriate for the 3D drift-diffusion (DD) simulations is proposed and it is demonstrated that the present model could properly take into account the threshold voltage variations in sub-0.1 /spl mu/m MOSFETs.

Enhancement of hot-electron generation rate in Schottky source metal–oxide–semiconductor field-effect transistors

Source-side hot-electron generation is experimentally demonstrated in Schottky source metal–oxide–semiconductor field-effect transistors (MOSFETs). An asymmetric n-type MOSFET having a CoSi2 layer in place of one of the n+ source/drain regions has been fabricated and intensively investigated. When the CoSi2 layer is used as the source, large gate current and negative-differential conductance (NDC) are simultaneously observed, whereas, when the n+ region is used as the source, both gate current and NDC are not observed. By comparing the device characteristics before and after the NDC observation, it is concluded that the gate current is due to hot electrons generated at the Schottky source side and the NDC is caused by trapped electrons in the oxide. These source-side hot electrons will open up the way to the realization of deca-nanoscaled high-speed devices.

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

A New Design Scheme for Logic Circuits with Single Electron Transistors

A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

Device modeling and simulations toward sub-10 nm semiconductor devices

This paper overviews the fundamental problems encountered in device modeling and simulations of sub-10 nm Si metal-oxide-semiconductor field-effect-transistors (MOSFETs). We focus on the two fundamental problems: the quantum effects and the effects associated with the long-range Coulomb potential. It is pointed out that these problems are profoundly related to the basic principles of device physics and even pose a question on the validity of the basic transport equation which the present device simulations are based on. We also review various approaches and methods taken to tackle those problems.

Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

Comprehensive Understanding of Electron and Hole Mobility Limited by Surface Roughness Scattering in Pure Oxides and Oxynitrides Based on Correlation Function of Surface Roughness.

A new model of the roughness correlation function S(r) has been proposed in order to explain the different behavior of high field mobility limited by surface roughness scattering, µSR, between electrons and holes in metal oxide semiconductor field effect transistors (MOSFETs) with oxynitrides. It has been shown, for the first time, that the change in electron and hole µSR associated with NO oxynitridation can be reasonably well explained by the appropriate choice of the form of S(r).

Scaling effects on gate leakage current

Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. This calculation is indispensable for reproducing the measured gate current-gate voltage characteristics in the device simulation. As a result, it is concluded that the scaling of the gate width cannot suppress the gate leak, even if the specification of the threshold voltage is relaxed in order to shrink the gate width. It is also found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.