Toshiyuki Takewaki

Electrical Properties of Giant‐Grain Copper Thin Films Formed by a Low Kinetic Energy Particle Process

Fomnation of giant-grain copper thin films on SiO 2 by a low-kinetic energy particle process followed by thermal annealing has been investigated. When Cu films are grown on SiO 2 by the process under a sufficient amount of energy deposition, they exhibit almost perfect crystal orientation conversion from Cu(111) to Cu(100) upon themnal annealing. Such crystal orientation conversion is accompanied by the giant grain growth in the film as large as 100 μm. With regard to these phenomena, the effects of the ion flux density and of the ion bombardment energy have been studied

Tradeoff Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects

We investigated tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects. A unique resistivity-measurement technique is proposed to detect influences due to impurity doping. Using this technique, we investigated the impacts of the impurity doping on three types of copper interconnects - cobalt-tungsten-phosphorous (CoWP) metal-cap interconnects, plasma-enhanced chemical-vapor-deposition self-aligned barrier interconnects, and CuAl alloy interconnects - and clarified the tradeoffs between the resistivity and the reliability. We found that the metal-cap interconnect shows not only high reliability but also outstanding efficiency with regard to the suppression of resistance increase due to impurity doping.

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

Evaluation of electromigration and stressmigration reliabilities of copper interconnects by a simple pulsed-current stressing technique

By using a simple pulsed-current stressing technique, we have demonstrated that both electromigration and stressmigration resistance of giant-grain Cu interconnects can be evaluated separately in a very efficient manner. From the results of such lifetests, it was found that the reliability of the the Cu interconnect is primarily determined by the stressmigration rather than by the electromigration.<<ETX>>

A Novel Resistivity Measurement Technique for Scaled-down Cu Interconnects Implemented to Reliability-focused Automobile Applications

A novel resistivity measurement technique has been proposed for scaled-down Cu interconnects viewing the high-reliability automobile applications. This technique enables to detect the interconnect resistivity dependence on impurity concentration, free from dimension dependence. Using this technique, we investigated impacts of impurity concentration on three types of Cu interconnects: 1) CoWP cap; 2) PECVD self-aligned barrier (PSAB); and 3) CuAl interconnects and clarified the tradeoffs between resistivity and reliability. We have found that CoWP cap shows not only high-reliability but also an outstanding efficiency in suppression of resistance increase due to impurity-induced scattering, indicating that it is the most viable candidate for automobile applications in 32nm generation and beyond

Accurate Modeling Method for Cu Interconnect

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.