Tzu-Ying Kuo

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.

An innovative chip-to-wafer and wafer-to-wafer stacking

Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept of three-dimensional integration of via-preformed silicon through wafers. Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design. The wafer/chip thickness used here was 150 mum and down to 50 mum. The result shows the benefits of this structure can provide more reliable wafer stacking without any voids. Not only the assembly accuracy of the joint between two chips/wafers can be reduced, but we can get improvement of the yield of the whole wafer during the wafer bonding process, even the thickness uniformity of the wafer is higher than 10%. The experiment confirmed that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module

Development and characterization of low cost ultrathin 3D interconnect

With the economic criteria and efficiency concern increasing, abundant through-hole vertical interconnections are playing the more and more important role in this area. The properties and characterization of through-hole vertical interconnects are the key issue results in the RC delay during the reliability tests for 3D high-density module packaging. ERSO recently works mainly focuses on the investigation of the quality of low cost interconnect fabrication technology to meet the reliability requirement for 3D chip stacking interconnects. In this paper, we elucidate the interconnect technology for a stacked system in package (SiP) test vehicle. Compared to the vertical interconnects developed recently, we provide an extremely low cost solution for both of silicon hole drilling process and electrical isolation within the hole. A PCB compatible electroplating technology was followed to fill the hole and shows void-free and low resistance result during this work. The chip thickness used here can be 150/spl mu/m and down to 20 /spl mu/m and still provide outstanding interconnect reliability during bending and thermal cycling test. We confirmed that the low cost 3D interconnects are potentially candidate for 3D chip stacking packaging.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

Thermal Effect Characterization of Laser-Ablated Silicon-Through Interconnect

As to the wafer through holes formation, methods such as reactive ion beam (RIE) and inductive coupled plasma (ICP) were used usually. In this paper, we use UV laser to study hole formation in silicon wafer. Siemens Dematic Microbeam 3205 laser machine with a 355nm wavelength was used in this study. Laser drilling is a non-contact manufacture method, it can apply high energy to a small spot (15mum focused beam diameter) to ablate and remove the material. The advantage of a UV laser process compared to lithography by masks is its capability of local alignment. While a mask has to be aligned to the whole panel, the laser can use local fiducial marks, allowing a higher accuracy and yield by laser drilling. We choose laser drilling process to make the efficient through holes in this paper. Hole drilling in silicon wafer by short pulse laser. Thermal and mechanical effects on silicon wafer induced by laser drilling were analyzed was characterized under optical microscopy (OM), scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS)

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.

Flexible and ultra-thin embedded chip package

An ultra-thin, flexible package was successfully demonstrated in this paper. The integration of semiconductor chip and flexible substrate, development of ultra-thin chip technology, and embedded chip technology are the key topics. For the purpose of bendable, the embedded chip should be thin enough. The chips were thinned to less than 20µm by mechanical grinding and plasma treatment process. Besides, the dicing before grinding (DBG) method was applied for segment of ultra-thin chips. The ultra-thin chip can be embedded into a thin polyimide material by lamination process and build-up layer coating without die attached film (DAF). Following, micro-via drilling process, metallization and patterning process realize electrical interconnections. A temporary rigid carrier substrate was used for handling ultrathin substrate during process. Finally, an ultra-thin, flexible package was accomplished by releasing from the carrier substrate. Using this novel process, the total thickness of flexible package is only 59µm. It can be easily bended, and the curvature radius of flexible package can reach 10mm without any cracks occurred. The static and dynamic bending tests were also done. The results show this ultra-thin and flexible package has good mechanical properties. Technologies and bending test results will be represented in this paper.

3D Chip-to-Chip Stacking with Through Silicon Interconnects

The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on LTSI confirm that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.

An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.