Ying-Ching Shih

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP

As the demands for high-density, high-speed, high-performance, and multi-function in portable electronic products, packaging technologies require significant improvement to bring out ICs performance and shrink the total module or package size. One representative technology is to embed active devices into an organic substrate by sequential build-up processes, for example, chip-in-polymer by IZM, bumpless build-up layer by Intel, and chip-in-substrate package (CiSP) by EOL/ITRI. Through embedding the semiconductor chip in the organic substrate, the package with very good electrical performance and good capability for system integration can be realized. In this research, DDRII memory was chosen as the CiSP test vehicle, and the designed structure provides better electrical and thermal performance. Several core techniques, such as wafer thinning, die bonding, high-flatness lamination, were well developed to embed DDRII-like thin chips (50 mum thick) into dielectric material on a carrier substrate. The PCB compatible laser drilling, via metallization, and patterning technologies were subsequently followed to form an electric path from chip-pad to outer, which provides shorter interconnection for the demand of fast electrical response application. Moreover, the vehicle was tested by lead-free reliability tests, inclusive of pre-condition (3 reflows at 260degC), level B thermal cycle, and 168 hrs PCT tests. The newest results of the reliability tests will be presented in the paper

TSV process using bottom-up Cu electroplating and its reliability test

TSV (through silicon via) is a core technology in 3D IC package. The micro vias can be made by etching or laser drilling. Standard processes for TSV filling begin with seed layer deposition, followed by blind vias copper electroplating. If the aspect ratio of the TSV is higher than 5:1, the costly MOCVD process needs to be used to deposit the seed layer with good step coverage. A special designed electroplating machine and solution for high aspect ratio copper electroplating is needed. Some researchers even use PRP (periodic reverse plating) for void free copper electroplating instead of traditional DC power supply.

3D stacked chip technology using bottom-up electroplated TSVs

In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle and the scallop at the sidewall of the vias. By using the bottom-up electroplating technology, we could fabricate the TSVs in much shorter process time to save the process cost. From the X-Ray images and the SEM pictures, the diameter of the vias is 5.3 micron meters and the length of the vias is 67 micron meters. The aspect ratio of the bottom-up electroplated TSVs is larger than 12 and all the vias are definitely void free. X-Ray image also shows the process yield is very high. After the thermal shock reliability test, the resistance measurement and the vias are fine from the SEM pictures. There is no crack found at the sidewall of the vias. After the TSV process, the bonded electrode continues to serve as electrode for the mask-less Sn electroplating. The electroplating current goes through the bottom electrode TSVs and the Sn is electroplated on the TSVs without mask define. Sn bump served as mechanical and electrical connection. We also demonstrate the dry etching process for wafer thinning on a 170°C thermal release tape with handling substrate. After the etching process, the thickness of the chip is about 5µm and then it is released from the handling substrate successfully. For thin wafer handling technology, we proposed a metal temporarily bonding technology. Au to Au bonding is used here for metal temporarily bonding. After the wafer thinning process, the sample could sustain high temperature process without crack and could be removed from the handling substrate after the process. This study also demonstrates the process flow for the 3D chip stacking by using the bottom-up electroplated TSVs. The handling substrate is removed by metal temporarily bonding technology and the interconnection is done by Cu/Sn bump. Based on this technology, the TSVs in the 3D chip stacking could be made in shorter electroplating time and low cost way by a traditional electroplater.

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288degC solder dipping and 260degC level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.

An innovative chip-to-wafer and wafer-to-wafer stacking

Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept of three-dimensional integration of via-preformed silicon through wafers. Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design. The wafer/chip thickness used here was 150 mum and down to 50 mum. The result shows the benefits of this structure can provide more reliable wafer stacking without any voids. Not only the assembly accuracy of the joint between two chips/wafers can be reduced, but we can get improvement of the yield of the whole wafer during the wafer bonding process, even the thickness uniformity of the wafer is higher than 10%. The experiment confirmed that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

Flexible and ultra-thin embedded chip package

An ultra-thin, flexible package was successfully demonstrated in this paper. The integration of semiconductor chip and flexible substrate, development of ultra-thin chip technology, and embedded chip technology are the key topics. For the purpose of bendable, the embedded chip should be thin enough. The chips were thinned to less than 20µm by mechanical grinding and plasma treatment process. Besides, the dicing before grinding (DBG) method was applied for segment of ultra-thin chips. The ultra-thin chip can be embedded into a thin polyimide material by lamination process and build-up layer coating without die attached film (DAF). Following, micro-via drilling process, metallization and patterning process realize electrical interconnections. A temporary rigid carrier substrate was used for handling ultrathin substrate during process. Finally, an ultra-thin, flexible package was accomplished by releasing from the carrier substrate. Using this novel process, the total thickness of flexible package is only 59µm. It can be easily bended, and the curvature radius of flexible package can reach 10mm without any cracks occurred. The static and dynamic bending tests were also done. The results show this ultra-thin and flexible package has good mechanical properties. Technologies and bending test results will be represented in this paper.

3D Chip-to-Chip Stacking with Through Silicon Interconnects

The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on LTSI confirm that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.

Manufacturing and stacking of ultra-thin film packages

This paper discloses an ultra-thin and highly flexible package with embedded active chips. In this structure, there are no any supporting and permanent substrates needed. A 3um copper foil with 18um carrier layer was used as temporal substrate. The carrier layer will be removed after chip embedded process. After patterning and etching processes, the temporal copper foil became the bottom circuit that will connect with the other Ultra-Thin Film Package(UTFP). Ultra thin chips with around 15∼20µm thickness were assembled directly on the structured Cu foils in a flip-chip fashion. The structured Cu foils were patterned by laser to enhance the wettability with solder. The gap between chip and copper foil was only about 15µm after the die bonding process. In order to fabricate the ultra thin chip, plasma dry etching was applied to release the stress induced during the grinding process and also made the chips strength higher. The strength of ultra thin chip with and without plasma treatment was also compared. Subsequently, the chips were embedded into highly elastic polyurethane materials, with a copper foil always laminated on the top. The resultant UTFP has a thickness of less than 80 µm. The process details on ultra-thin wafer manufacturing, ultra-thin chip bonding, fine gap with underfill dispensing, thin chip lamination, laser drilling, laser patterning and stacking are also disclosed in this paper. The stacking process of UTFP is also a key technology in this paper. Because the stacking temperature is controlled below 150°C, Anisotropic Conductive Film(ACF) material was used as the connecting medium. So far, the single UTFP has passed static bending test for 200 hours and dynamic bending test for 500 cycles under 5mm bending curvature radius. In the future, the reliability tests which include TCT and TAST tests will be also executed, but not shown in this paper. The numerical simulation method will also be revealed to figure out the most critical point during UTFP fabrication process and the stacking process.