Yuan-Chang Lee

A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via

To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled from the wafer backside.

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288degC solder dipping and 260degC level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Flexible Electronic-Optical Local Bus Modules to the Board-to-Board, Board-to-Chip, and Chip-to-Chip Optical Interconnection

In this paper, a flexible active E/O local bus module using multi-mode optical transmission is proposed to perform board-to-board, chip-to-chip, or board-to-chip optical interconnection with compatibility to traditionally electrical interfaces. In this proposed scheme, high speed modules or chips on tradition printed circuit board (PCB) can be directly interconnected through a flexible active E/O cable which can actively convert high speed signals to/from optical forms and then transmit optical signals through the optical waveguide layer. A 17-cm long prototyping of the proposed E/O local bus module is developed here to demonstrate the feasibility of short reach optical interconnection in board level applications

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Characterization of organic multi‐mode optical waveguides for electro‐optical printed circuit boards (EOPCB)

In this paper, characteristics of optical propagation of the vertical cavity surface emitting laser (850 nm VCSEL) through organic multi-mode optical waveguides are studied. Based on the typical optical loss measurement and the beam profile analysis of optical power distribution, the variation and co-relation between the VCSEL light source and the waveguide outputs are explored. Key factors of waveguide design for EOPCB integration, including the coupling scheme, geometric dimensions, bending, thermal effects, reliability, and etc., are further characterized based on experimental results. A 2.5Gbps optical interconnection prototype using film-type organic array waveguide is also demonstrated here for short reach data-communication at 12 cm.

Characterization of organic multi-mode optical waveguides for the electro-optical printed circuit board (EOPCB)

In this paper, characteristics of optical propagation of the vertical cavity surface emitting laser (850 nm VCSEL) through organic multi-mode optical waveguides are studied. Based on the typical optical loss measurement and the beam profile analysis of optical power distribution, the variation and co-relation between the VCSEL light source and the waveguide outputs are explored. Key factors of waveguide design for EOPCB integration, including the coupling scheme, geometric dimensions, bending, thermal effects, reliability, and etc., are further characterized based on experimental results. A 2.5Gbps optical interconnection prototype using film-type organic array waveguide is also demonstrated here for short reach data-communication at 12 cm.

Process integration for backside illuminated image sensor stacked with Analog-to-Digital Conversion chip

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500 μm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 μm after thinning and the total thickness variation is around 1 μm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.