Ui-Sik Kim

Highly thermal robust NiSi for nanoscale MOSFETs utilizing a novel hydrogen plasma immersion ion implantation and Ni-Co-TiN tri-layer

In this letter, hydrogen plasma immersion ion implantation (H PIII) with Ni-Co-TiN tri-layer is introduced for the first time to enhance the thermal stability of the Ni-silicide for nanoscale CMOS technology. The Ni-silicided poly-Si gate and source/drain showed stable sheet resistance in spite of 650/spl deg/C, 30 min post-silicidation annealing. The junction leakage current is even improved a lot without degradation of device performance using the proposed method.

Novel Nitrogen Doped Ni Self-Alingned Silicide Process for Nanoscale Complementary Metal Oxide Semiconductor Technology

In this paper, 1%-nitrogen doped nickel was proposed to improve the thermal stability of Ni-silicide for nano-scale N-type Metal Oxide Semiconductor Field Effect Transistor. It is shown that thermal stability of nickel silicide is improved a lot by the Nitrogen incorporation in NiSi layer using the 1%-nitrogen doped nickel target. Even after post-silicidation annealing at 650°C for 30 min, the low resistivity NiSi with low junction leakage current can be achieved. Moreover, improved device characteristics such as threshold voltage, transconductance, and on-off current, subthreshold slope were obtained in 80 nm NMOSFET.

Co-Induced Low-Temperature Silicidation of Ni Germanosilicide Using NiPt Alloy and the Effect of Ge Ratio on Thermal Stability

In this paper, novel Ni germanosilicide technology using NiPt alloy and Co overlayer has been proposed. Using the Co overlayer after NiPt deposition on Si1-xGex, the formation temperature of low resistive Ni germanosilicide is lowered with high thermal stability. The thermal stability of Ni germanosilicide with different Ge fraction in is also characterized. The sheet resistance degrades as increasing the Ge fraction (x) in Si1-xGex when NiPt/TiN is used. However, using the Co overlayer, the sheet resistance property among Ni germanosilicide formed with different Ge fraction is improved greatly compared with those of NiPt/TiN case (without Co overlayer). Therefore, low-temperature formation of highly thermal robust Ni germanosilicide can be achieved through the NiPt/Co/TiN tri-layer.

Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology

A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700°C, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650°C, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes.

Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application

NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.

Ni/Co/Ni/TiN structure for highly thermal immune NiSi for CMOSFETs application

In this paper, a novel Ni/Co/Ni/TiN structure to improve the thermal stability of NiSi by forming highly thermal stable ternary phase, i.e., (Co/sub x/Ni/sub 1-x/)Si/sub 2/ especially at the top region of NiSi is proposed. The Ni/Co/Ni/TiN structure is very promising for the nanoscale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes.

Highly thermal robust Ni-germanosilicide utilizing NiPt/Co/TiN tri-layer for CMOS application

Highly thermal robust Ni-germanosilicide has been developed using the novel NiPt/Co/TiN tri-layer. Ni-germanosilicide properties were characterized with different source/drain dopants and Ge concentrations for nanoscale CMOSFETs application. The sheet resistance was degraded as the Ge concentration increases in Si/sub 1-x/Ge/sub x/. Low temperature silicidation and wide range of RTP process window are achieved as well as the improvement of the thermal stability according to different dopant types by the subsequent Co and TiN capping layer above NiPt on Si/sub 1-x/Ge/sub x/.