Vikram Pavate

Correlation between aluminum alloy sputtering target metallurgical characteristics, arc initiation, and in-film defect intensity

Increasing levels of metallization, shrinking device geometries, and stringent defect density requirements have led to a continuous focus in the semiconductor manufacturing community to reduce defects generated during metal deposition by PVD techniques. Of particular interest in the metallization community is the reduction in in-film defect density in sputtered aluminum films. Pareto analysis of in-film defects in currently used interconnect metallization schemes suggest that a considerable portion of the in-film defects (up to 50%) are caused by unipolar arcing during aluminum deposition. Due to their unusual molten appearance, these defects are commonly referred to as splats. These defects can be as large as 500 micrometers , and due to their frequency of occurrence and size can significantly impact device yield in a manufacturing environment. Systematic investigations have revealed that the formation of splats, due to unipolar arcing, can be strongly correlated to the metallurgy of the aluminum alloy targets used during aluminum sputter deposition. The presence of undesirable metallurgical attributes such as alumina inclusions, porosity, oxygen content etc. are the primary causes for the occurrence of unipolar arcing. These undesirable metallurgical attributes appear to be the result of the manufacturing processes used to manufacture the aluminum alloy targets. The results of this study indicate that significant improvement in defect generation due to unipolar arcing during sputter deposition of aluminum films, and hence an improvement in device yield, is possible by reduction/elimination of the various undesirable metallurgical attributes in the aluminum alloy targets.

IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects

Filling of high aspect ratio vias with electroplated copper requires smooth and continuous seed layer whereas prevention of copper diffusion into the adjacent dielectric requires adequate coverage of the barrier along the via sidewalls. Conventional PVD DC magnetron techniques were found to be inadequate for this application, because of insufficient step coverage especially that of Cu on the sidewalls of the high aspect ratio vias, and its agglomeration into discontinuous islands. Ionized metal plasma (IMP) based PVD technology provided superior step coverage of Ta and Cu because of the directionality of the deposited atoms and utilization of ion bombardment to sputter material from the bottom of the via to the sidewalls, thus yielding continuous and conformal barrier and seed layers. Furthermore, the seed layer morphology especially the roughness of the film on the sidewall was found to be quite sensitive to the deposition temperature. The seed layer thickness and film morphology, as well as other deposition parameters as the ratio of coil RF & target DC plasma powers, Ar sputtering pressure, wafer bias and the Ar sputter etch prior to barrier deposition, were all found to affect the subsequent via filling by electroplating. Optimization of the processes enabled filling of high aspect ratio vias. Manufacturability and the process window for the barrier/seed layer processes was evaluated by extended runs and DOEs. The technology was successfully integrated into a multilevel interconnect scheme utilizing Cu plugs, and Cu damascene lines. The via resistance of the Cu plug using this metallization scheme, was found to be significantly lower than that of W plug currently used for Al interconnects. The cost of ownership (COO) of the IMP Ta/Cu seed layer was determined to be significantly lower compared to the current state-of- the-art IMP Ti/CVD TiN liner for W plug.

Ultrathin integrated ion metal plasma titanium and metallorganic titanium nitride liners for sub 0.18 μm W based metallization schemes for >500 MHz microprocessors

This study will specifically address the results of integrating IMP Ti and MOCVD TiN on a high vacuum system. Results of design of experiments used for process characterization and optimizing device parametric such as contact and via resistance will be discussed, in particular with respect to unlanded via schemes. Finally, Cost of Ownership calculations will be presented in comparison to conventional PVD technologies. In summary, the integration of IMP Ti and MOCVD TiN enables the deposition of a highly cost effective, low resistivity, ultra-thin, and low- temperature liners for sub 0.18 micrometers technology node thereby enabling > 500 MHz microprocessor technology.

Integrated arc suppression unit for defect reduction in PVD applications

Arcing between the target and plasma during PVD deposition causes substantial damage to the target and splats and other contamination on the deposited films. Arc-related damages and defects are frequently encountered in microelectronics manufacturing and contributes largely to reduced wafer yields. Arcing is caused largely by the charge buildup at the contaminated sites on the target surface that contains either nonconducting inclusions or nodules. Arc suppression is a key issue for defect reduction, yield improvement and for reliable high quality metallization. An Integrated Arc Suppression Unit (IASU) has been designed for Endura HP PVDTM sputtering sources. The integrated design reduces cable length from unit to source and reduces electrical energy stored in the cable. Active arc handling mode, proactive arc prevention mode, and passive by-pass arc counting mode are incorporated into the same unit. The active mode is designed to quickly respond to chamber conditions, like a large chamber voltage drop, that signals a arc. The self run mode is designed to proactively prevent arc formation by pulsing and reversing target voltage at 50 kHz. The design of the IASU, also called mini small package arc repression circuit--low energy unit (mini Sparc-le), has been optimized for various DC magnetron sources, plasma stability, chamber impedance, power matching, CE MARK test, and power dissipation. Process characterization with Ti, TiN and Al sputtering indicates that the unit has little adverse impact on film properties. Mini Sparc-le unit has been shown here to significantly reduce splats occurrence in Al sputtering. Marathon test of the unit with Ti/TiN test demonstrated the units reliability and its ability to reduce sensitivity of defects to target characteristics.

Integrated IMP Ti and MOCVD TiN for 300-mm W barrier and liner for sub-0.18-μm IC processing

The combination of IMP Ti and CVD TiN is well established for use as W-adhesion films for 200 mm wafers. The advantage of this unique PVD/CVD integrated solution provides the superior Ti bottom coverage by IMP Ti and conformal TiN coverage from MOCVD TiN. A 300 mm liner and barrier system with integrated IMP Ti, MOCVD TiN has also been developed on Endura mainframe. Scale-up to 300 mm poses several unique challenges to both CVD and PVD processes. Additionally, since 300 mm processing will likely be implemented at sub 0.18 micrometers mode, ultra-thin liners will be required for superior device performance. This paper discusses the process characterization of the 300 mm IMP Ti and MOCVD TiN for thin films (<200 A Ti and <100 A TiN). The Rs and Rs uniformity of 300 mm IMP Ti and CVD TiN were shown to be comparable with the results achieved for 200 mm. Laser acoustic wave spectrometry measurement of thickness and thickness uniformity of ultra-thin Ti (50 A) and TiN (50 A) will also be presented. Cross sectional TEM study shows superior Ti bottom coverage and conformal TiN coverage were also achieved with the integrated 300 mm IMP Ti/CVD TiN process. Process stability was demonstrated with 250-wafer run. The process results of 300 mm Ar sputtering preclean and degas will also be presented in the paper.