M. ter Beek

High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.

Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits

Triggering structures BJT, SCR and bi-directional SCR for high voltage BiCMOS process onchip ESD protection have been developed and analyzed using physical process and device simulation and pulse measurements. A ten-fold increase in the protection levels compared to the reference BJT structures have been demonstrated using a cylindrical lateral SCR and bidirectional SCR.

Physical limitation of the cascoded snapback NMOS ESD protection capability due to the non-uniform turn-off

The nonlinear effects and physical failure mechanism in over-voltage protection NMOS snapback structures during ESD operation have been analyzed with the use of experimental test structures as well as process and device simulations. A phenomenological explanation has been provided to account for the effect due to substrate type and the use of a so-called ESD implant. A generic design solution for the cascoded snapback NMOS structure suitable for 5-V tolerant I/O applications is proposed, one that delivers robust operation and eliminates the requirement for an additional ESD implant.

ESD protection window targeting using LDMOS-SCR devices with PWELL-NWELL super-junction

A variety of analog applications require an extension of the low-voltage process capabilities towards 12-20 volts or higher for a limited number of pins. The most cost effective way to achieve this is to extend low-voltage sub-micron CMOS processes by the implementation of extended voltage lateral BJT, self-aligned lateral DMOS (LDMOS) and non-self aligned devices with an extended drain, either using existing CMOS process regions (Dolny, G.M. et al., 1986) or by adding a few extra regions. The ESD protection of these high-voltage devices in the low-voltage process presents a new challenge. The most robust way to protect the extended voltage LDMOS devices is by the implementation of a silicon controlled rectifier LDMOS-SCR structure (Concannon, A. et al., 2004). The paper focuses on a device level solution for the control of both the breakdown voltage and the triggering characteristics of the extended voltage ESD devices. This was achieved by the use of super-junctions (multi-RESURF) (Deboy, G. et al., 1998; Xu, S. et al., 2000) and diluted-junctions (Vashchenko, V.A. et al., 2004) widely used for discrete power devices.

LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits

Abstract The results of a numerical and experimental study aimed at increasing the holding on-state voltage of a low-voltage triggered silicon controlled rectifier are presented. Using TCAD numerical simulations two solutions are presented that are based on emitter injection control by the modification of the emitter–drain area ratio and by the addition of internal diodes in the emitter line. Experimental data generated in a 0.18 μm CMOS technology demonstrate the effectiveness of the new low-voltage triggered silicon controlled rectifier (LVTSCR) structures and validates the simulation results. It has been demonstrated that for the LVTSCR structures with high holding voltage the electrostatic discharge efficiency is 3–5 times higher than that of a conventional grounded gate snapback NMOS and simultaneously has 50% lower RF load capacitance.

Implementation of 60V tolerant dual direction ESD protection in 5V BiCMOS process for automotive application

A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.

A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection

The practical goal of this study is to develop an efficient design solution for the control of the holding voltage of thyristor-type structures (ones operating in the left part of S-shape I-V characteristic), thereby making them suitable for use in mixed-signal and in power supply protection circuits. This specific design is applied to the cascoded LVTSCR structures and validated on the basis of ESD test structures and I/O cells. The research objective was to control the avalanche-injection conductivity modulation by the emitter injection of the device level, thereby achieving control of the section of the S-shape I-V curve responsible for the holding voltage.

ESD protection of the high voltage tolerant pins in low-voltage BiCMOS processes

A methodology. for achieving ESD devices by increasing the breakdown voltage of the protection of high voltage pins in a low voltage blocking junctions for ESD devices in 0.5pm technology is presented. The methodology utilizes eilicient mask level control of both the blocking BiCMOS and CMOS processes. lr Hlgh Voltage junction and the triggering characteristics of the *5v . .. . . . t.. . .. . , ESD devices without the addition or chance in anv -. process steps. The methodology was validated by numerical simulation and experimental measurements for the case of dualdirection SOV tolerant onship ESD protection of thin fh resistors in a N BiCMOS process. The methodology was also applied to the case of tnrnon voltage increase of an extended drain SCR ESD protection device in a 5V CMOS process.

Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design

The objective of this study is to find a generic design solution for the cascoded snapback NMOS that delivers robust operation and eliminates the requirement for an additional ESD implant. In addition, the research goal of this study is to understand the physical failure mechanism, taking into account the non-linear effects of NMOS snapback, and to provide, at a minimum, a phenomenological explanation of the observed trends resulting from the analysis of Si based experiments.

Emitter injection control in LVTSCR for latch-up free ESD protection

A low-voltage triggered silicon controlled rectifier with optimized holding voltage for ESD protection, has been developed and is demonstrated in a 0.18 /spl mu/m CMOS technology. Process and device simulation is used to determine the relationship between electrical parameters and geometrical features. Pulse measurements of silicon test structures demonstrate that the ESD efficiency of this approach is 3-5 times that of a conventional grounded gate snapback n-MOS with the same holding voltage.