Vyshnavi Suntharalingam

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

Scaling Three-Dimensional SOI Integrated-Circuit Technology

In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +/--0.5 mum wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a back-metal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.

Back-illuminated three-dimensionally integrated CMOS image sensors for scientific applications

SOI-based active pixel image sensors have been built in both monolithic and vertically interconnected pixel technologies. The latter easily supports the inclusion of more complex pixel circuitry without compromising pixel fill factor. A wafer-scale back-illumination process is used to achieve 100% fill factor photodiodes. Results from 256 x 256 and 1024 x 1024 pixel arrays are presented, with discussion of dark current improvement in the differing technologies.

Monolithic 3.3 V CCD/SOI-CMOS imager technology

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCDs, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1/spl times/10/sup -5/ and well capacities of more than 100,000 electrons with 3.3-V clocks and 8/spl times/8-/spl mu/m pixels. Fully depleted 0.35-/spl mu/m SOI-CMOS ring oscillators have stage delay of 48 ps at 3.3 V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.

Toward fast, low-noise, low-power digital CCDs for Lynx and other high-energy astrophysics missions

Future X-ray missions such as Lynx require large-format imaging detectors with performance at least as good as the best current-generation devices but with much higher readout rates. We are investigating a Digital CCD detector architecture, under development at MIT Lincoln Laboratory, for use in such missions. This architecture features a CMOS-compatible detector integrated with parallel CMOS signal processing chains. Fast, low-noise amplifiers and highly parallel signal processing provide the high frame-rates required. CMOS-compatibility of the CCD provides low-power charge transfer and signal processing. We report on the performance of CMOS-compatible test CCDs read at rates up to 5 Mpix s−1 (50 times faster than Chandra ACIS CCDs), with transfer clock swings as low as ±1.5 V (power/area < 10% of that of ACIS CCDs). We measure read noise below 6 electrons RMS at 2.5 MHz and X-ray spectral resolution better than 150 eV FWHM at 5.9 keV for single-pixel events. We discuss expected detector radiation tolerance at these relatively high transfer rates. We point out that the high pixel ’aspect ratio’ (depletion-depth : pixel size ≈ 9 : 1) of our test devices is similar to that expected for Lynx detectors, and illustrate some of the implications of this geometry for X-ray performance and noise requirements.

Deep-Trench Process Technology for Three-Dimensionally Integrated SOI-Based Image Sensors

Large arrays of scientific imaging devices are in demand for wide-field-of-view imaging systems. We present a deep-trench process technology that enables the fabrication of SOI-based, 3-D-integrated, 4-side-abuttable image sensor tiles that can be assembled into large-area focal plane arrays. We demonstrate low-leakage, functional devices with 13.4-mum spacing between tile edge and the first imaging pixel.

SLOTFET fabrication of self-aligned sub-100-nm fully-depleted SOI CMOS

In recent years, substantial efforts have been directed toward development of SOI CMOS circuits, with gate lengths scaled to the sub-100 nm regime. These efforts have been motivated by the potential of low voltage, low power, and high speed performance of SOI CMOS in comparison to bulk devices (Hu, 1998). In this work, we describe a new sub-100 nm CMOS SLOTFET fabrication process using conventional 0.25 /spl mu/m SOI CMOS processing techniques with DUV 248 nm photolithography, and we present experimentally measured p- and n-MOSFET characteristics. In comparison to an existing fully-depleted 0.25 /spl mu/m SOI CMOS process (Liu et al, 1998), the SLOTFET process offers several important advantages, including (i) self aligned T-gate, allowing lower gate resistance required for high-f/sub max/ RF transistors, (ii) island spacers, suppressing parasitic sidewall transistors, (iii) recessed SOI channel region, minimizing short-channel effects and drain-induced-barrier lowering (DIBL), and (iv) raised source-drain region, allowing the maximum advantage of a cobalt salicide process for low source-drain series resistance. In the first SLOTFET fabrication run, both p- and n-MOS devices exhibited very promising sub-threshold slopes, drive current, off-state leakage, and DIBL; fine tuning is needed to optimize drive current, threshold voltage, and series resistance.

Development of CCDs for REXIS on OSIRIS-REx

The Regolith x-ray Imaging Spectrometer (REXIS) is a coded-aperture soft x-ray imaging instrument on the OSIRIS-REx spacecraft to be launched in 2016. The spacecraft will fly to and orbit the near-Earth asteroid Bennu, while REXIS maps the elemental distribution on the asteroid using x-ray fluorescence. The detector consists of a 2×2 array of backilluminated 1k×1k frame transfer CCDs with a flight heritage to Suzaku and Chandra. The back surface has a thin p+-doped layer deposited by molecular-beam epitaxy (MBE) for maximum quantum efficiency and energy resolution at low x-ray energies. The CCDs also feature an integrated optical-blocking filter (OBF) to suppress visible and near-infrared light. The OBF is an aluminum film deposited directly on the CCD back surface and is mechanically more robust and less absorptive of x-rays than the conventional free-standing aluminum-coated polymer films. The CCDs have charge transfer inefficiencies of less than 10-6, and dark current of 1e-/pixel/second at the REXIS operating temperature of –60 °C. The resulting spectral resolution is 115 eV at 2 KeV. The extinction ratio of the filter is ~1012 at 625 nm.