Wallace P. Printz

Advances and Challenges in Dual-Tone Development Process Optimization

The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch node and beyond. Significant improvements in immersion lithography have allowed extension of optical lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost, along with technical capability, will dictate which candidate is adopted by the industry. Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone development was reported as early as in the late 1990s by Asano.2 The basic principle of dual-tone imaging involves processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent) developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many challenges that must be overcome and understood in order to make it a manufacturing solution. This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner. Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are presented.

Line-pattern collapse mitigation status for EUV at 32nm HP and below

Line pattern collapse (LPC) becomes a critical concern as integrated circuit fabrication continues to advance towards the 22 nm node and below. Tokyo Electron Limited (TEL) has been investigating LPC mitigation methods for many years [1]. These mitigation methods include surfactant rinses to help reduce surface tension and Laplace pressures forces that accompany traditional DIW rinses. However, the ability to explore LPC mitigation techniques at EUV dimensions is experimentally limited by the cost and availability of EUV exposures. With this in mind, TEL has adopted a combined experimental and simulation approach to further explore LPC mitigation methods. Several analytical models have been proposed [2, 3, 4] for a LPC simulation approach. However, the analytical models based on Euler beam theory are limited in the complexity of profile and material assumptions. Euler beam based models are also now questionable because they are outside the beam theorys intended aspect ratio regime [5]. The authors explore the use of finite element models in addition to Euler beam theory based models to understand resist collapse under typical EUV patterning conditions. The versatility of current finite element techniques allows for exploration of resist material property effects, profile and geometry effects, surface versus bulk modulus effects, and rinse and surfactant rinse effects. This paper will discuss pattern-collapse trends and offers critical learning from this simulation approach combined with experimental results from an EUV exposure system and TEL CLEAN TRACK ACTTM 12 platform, utilizing state of the art collapse mitigation methods.

Advanced Cryogenic Aerosol Cleaning: Small Particle Removal and Damage-Free Performance

The performance of a new cryogenic aerosol process was evaluated for cleaning nanoparticles and providing damage-free processing. Particle Removal Efficiency (PRE) tests conducted with wet deposited 40 nm, 30 nm and 18 nm silica particles on 300 mm wafers demonstrated cleaning efficiencies above 80%. Damage-free capability of the cryogenic aerosol process was evaluated with poly-silicon lines with an aspect ratio of approximately 9:1. These results highlight the potential of this new cryogenic aerosol to provide semiconductor device yield benefits by reducing small particulate contamination without causing pattern damage.