Wei-Hao Wu

Physical and Electrical Characteristics of F- and C-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

This work compares the physical and electrical properties of two species of inorganie low dielectric constant (low-k) chemical vapor deposited (CVD) oxides, F-doped fluorinated silicate glass (FSG, k = 3.5) and C-doped organosilicate glass (OSG, k - 2.9), Experimental results indicate that FSG has a higher thermal stability (>600°C) than OSG (500°C), based on the results of thermal annealing for 30 min in an N 2 ambient. The degradation of the low-k property in OSG is mainly due to the thermal decomposition of methyl (-CH 3 ) groups at temperatures above 500°C. For the Cu gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor (MIS) capacitors. Cu penetration was observed in both FSG and OSG after the MIS capacitors were bias-lemperature stressed at 250 and 150°C, respectively, with an effective applied field of 0.8 MV/cm. Specifically, Cu appeared to drift more readily in OSG than in FSG, presumably because OSG has a more porous and less dense structure than FSG. The Cu permeation can he impeded by a thin nitride (SiN) harrier layer.

Physical and Electrical Characteristics of Methylsilane- and Trimethylsilane-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

This work investigates the physical and electrical properties of two species of inorganic C-doped low dielectric constant (low-k) chemical vapor deposited (CVD) organosilicate glasses (OSGs, α-SiCO:H). They are both deposited by plasma-enhanced CVD (PECVD) processes using methylsilane [(CH 3 )SiH 3 , 1 MS]- and trimethylsilane [(CH 3 ) 3 SiH, 3 MS]-based gases as the reagents. and are designated as OSGI and OSG2, respectively, Experimental results indicate that the thermal stability temperature of OSG1 is 500°C, while that of OSG2 is 600°C, based on the results of thermal annealing for 30 min in an N 2 ambient. The deterioration of the low-k property in OSG1 is predominately duc to the thermal decomposition at temperatures above 500°C of methyl (-CH 3 ) groups, which are introduced to lower the density and polarizability of OSGs. For the Cu-gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor (MIS) capacitors, Cu permeation was observed in both OSG1 and OSG2 after the MIS eapacitors were bias-temperature stressed at 150°C with an effective applied field of 0.8 MV/cm. Moreover, Cu appeared to drift more readily in OSGI than in OSG2. presumably hecause OSGI has a more porous and less cross-linked structure than OSG2. The Cu penetration can he mitigated by a thin nitride dielectric barrier.

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

Physical and Barrier Properties of Plasma Enhanced Chemical Vapor Deposition α-SiC:N:H Films

In this work, we investigate the thermal stability and physical and barrier properties of three species of plasma enhanced chemical vapor deposition (PECVD) α-SiC:N:H silicon carbide films with different carbon and nitrogen contents and dielectric constants less than a value of 5.5. For comparison, one species of α-SiN:H film with a k value of 7.2 is also studied. It is found that the dielectric constant decreases with increasing content of carbon and decreasing content of nitrogen in the α-SiC:N:H film. All of the three species of α-SiC:N:H and the one species of α-SiN:H films are thermally stable at temperatures up to 500°C. However, degraded barrier capability and moisture resistance were observed for the α-SiC:N:H film with a k value of 3.5, which has a C/Si atomic ratio of 0.875. This is presumably due to the poorly crosslinked molecular structure and porosity enhancement caused by the abundant amount of carbon in the α-SiC:N:H film.

Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric

This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL). In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG. An appropriate ESL of sufficient thickness is essential to reduce the leakage for application to a Cu damascene integration scheme.This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL). In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG. An appropriate ESL of sufficient thickness is essential to reduce the leakage for application to a Cu damascene integration scheme.

Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK

This work investigates the dielectric and barrier properties of two species of organic aromatic low dielectric constant (low-k) polymers, namely, FLARE and SiLK. Experimental results indicate that both of the low-k polymers exhibit acceptable thermal stability with respect to a thermal annealing at 400°C for 8 h in an N 2 ambient. Moreover, they show a good dielectric barrier property against Cu penetration under bias-temperature stressing (BTS) at 150°C with an applied effective field of 0.8 MV/cm. Nevertheless, an anomalous instability of the capacitance-voltage curve was observed for the first time under BTS. This finding is explained by the proposed model of stress induced dielectric polarization charges within these organic aromatic polymers. The polarization instability may seriously degrade the long term reliability of cireuit operations.

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer

Transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO2 high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10-8- 10-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling

\hbox{HfO}_{2}/\hbox{SiO}_{2}

The electrical characteristics of HfSiO/SiO/sub 2/ high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.

High-

This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.