Woo-Hyeong Lee

Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology

The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement.<<ETX>>

A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.

Partial-SOI isolation structure for reduced bipolar transistor parasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.<<ETX>>

Single crystal emitter gap for epitaxial Si- and SiGe-base transistors

An epitaxial base bipolar technology has been used for fabrication of graded SiGe-based HBTs (heterojunction bipolar transistors) or Si-base pseudo-HBTs with a self-aligned in-situ doped n-type low-temperature epitaxial (LTE) emitter. The thin LTE emitter provides an EB junction with low tunneling current and low capacitance in a n+ poly/n/p+/n thin base HBT design with very high base doping. The authors report on Si and SiGe devices utilizing a 40 nm P doped LTE emitter with an n+ poly contact and silicided p+ poly extrinsic base contact. Nearly ideal DC characteristics were obtained for a device with a peak base doping concentration of over 1*10/sup 19/ cm/sup -3/. 44 GHz f/sub T/ devices with an AC base resistance of only 150 Omega were used to fabricate 24 ps ECL (emitter coupled logic) and 19 ps NTL ring oscillators to demonstrate the performance potential of the structure.<<ETX>>

Characterization of contact module failure mechanisms for SOI technology using E-beam inspection and in-line TEM

Electron-beam inspection (eBI) of the contact (CA) module for silicon-on-insulator (SOI) technology is discussed in this paper. Voltage contrast is used to detect CA opens in the SRAM and both CA opens and shorts in special test structures. The inspection is performed after the tungsten chemical mechanical planarization (W CMP) step. In-line transmission electron microscope (TEM) samples at select defect sites are then prepared and imaged to determine the failure mechanism. This methodology greatly enhances yield learning and provides quick feedback for lithography and etch process adjustments.

An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS

CMOS VCOs have been implemented for mm-wave applications [1–7], however, as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance, and it suffers from the steep VCO loop gain. Taking advantage of parallelism, using an array of VCOs is emerging as an alternative technique to implement a wide-band VCO (Fig. 16.3.1). While nanometer CMOS technology is becoming the next generation RF and mm-wave platform (because of high-speed performance due to technology scaling and and SoC integration capability), costly technology developments and mask sets further promote the use of array-based VCOs to expedite yield learning and circuit-development cycle. However, a VCO array requires more circuit area. Conventional designs are not scalable because of their size, cost, and complications for signal delivery. Technology scaling for mm-wave SoC is driven by the high-speed device performance while digital systems benefit from increased device density. In mm-wave applications, passive components, especially inductors, are responsible for area budget, since their area is not scaled with the technology. Taking advantage of nanometer FETs, the presented complementary LC-VCO is attractive for VCO arrays. It uses an LC-tank and its area is minimal and highly scalable. The use of state-of-the-art nanometer CMOS technology is essential to retain high-speed design margin for mm-wave circuits and provisions are required to make the complementary LC-VCO more scalable and manufacturable against the process variability and technology uncertainty. After all, the VCO array provides mm-wave-component performance-variability metrics as a feedback to the technology foundry. Such components are difficult and expensive to characterize and the required on-chip probe pads waste silicon area.

Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction

We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minimizing systematic ACV. Thermally-driven ACV was identified as a major mechanism in 32nm SOI technology. An optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power-performance trade-off.

Perimeter effects in small geometry bipolar transistors

The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<<ETX>>

Novel Bipolar Transistor Isolation Structure Using Combined Selective Epitaxial Growth and Planarization Technique

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.