Y. Akasaka

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi/sub 2/. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 mu m. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule. >

Three-dimensional topography simulation model: etching and lithography

An etching model in which topography is derived by solving a modified diffusion equation is introduced. This model is simple and makes it possible to simulate three-dimensional (3-D) topography accurately and quickly. Based on this model, a 3-D topography simulator which can be applied in the development of photolithography and isotropic/anisotropic etching has been developed. With this simulator, it is possible to simulate the series processes and multilayer etching, such as contact hole and trench etching. By simulating photolithography, diffraction and standing-wave effects can be found clearly in the 3-D topography of the developed photoresist. In the case of an etching process which is restricted by diffusion, the dependence of the etch front topography on the window width of the mask is examined. >

Structure design for submicron MOSFET on ultra thin SOI

In order to overcome the degradation of source-to-drain breakdown voltage (BV/sub dso/) in ultrathin SOI MOSFETs due to parasitic bipolar action, a gate overlapped LDD (lightly doped drain) structure was introduced for drain engineering. By the reduction of drain electric field and parasitic resistance at the source n/sup -/ region, the breakdown voltage was improved while keeping current drivability. The effect of channel doping level on BV/sub dso/ that affects the parasitic bipolar current gain was also investigated. Considering these two factors, guidelines for the structure design of submicron MOSFETs on ultrathin SOI are presented.<<ETX>>

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<<ETX>>

New topography expression model and 3D topography simulation of Al sputter deposition, etching, and photolithography

It is shown that the material surface can be described by the constant concentration area (the contour surface), by using the continuity principle at the material surface and considering the essential property of the material surface. Based on this model and the conservation of mass, the authors present a simulation algorithm and develop a 3D topography simulator (3D MULSS: Three-Dimensional Multi Layer Shape Simulator). It is demonstrated that this simulator can simulate the coverage of Al sputter deposition accurately, by comparing simulations and experimental results. 3D MULSS can also simulate the sequential processes of deposition, etching, and photolithography in three dimensions. In addition, it is shown that the proposed model can be applied to the surface tension by the 2D simulation of reflow.<<ETX>>

Salicide (self-aligned silicide) technology for ultra thin SIMOX MOSFETs

Summary form only given. A study of the TiSi/sub 2/-Si material system in ultrathin SIMOX MOSFETs and their electrical characteristics are discussed. Starting materials were separation by implantation of oxygen (SIMOX) wafers formed by oxygen ion implantation under conditions of 180 to 200 keV, 1.8 to 2.2*10/sup 18//cm/sup 2/, and 1350 degrees C, 30 min. annealing. The CMOS process was performed with the standard gate length of 1 mu m and LOCOS isolation. The sputtered Ti film on polysilicon gate electrodes and source/drain regions outside the oxide sidewall spacers was reacted with Si to form TiSi/sub 2/ by the two-step rapid thermal annealing (RTA) method. SIMOX films at the end of the process were 65 nm to 125 nm thick, depending on O/sup +/ doses. XTEM measurements indicated that the TiSi/sub 2/-Si interface by silicidation proceeded into the silicon films as the initial thickness of the Ti film was increased, and silicon films were fully silicided down to the underlying SiO/sub 2/ surface at Ti film thickness of 45 nm. Accordingly, both n and p source and drain sheet resistances were reduced from a few hundreds ohm/square (without silicide) to about 2 ohm/square. It was also found that some voids existed at the TiSi/sub 2/-Si interface just beneath the outside edge of the oxide spacer in the MOSFET structure, and a small portion of TiSi/sub 2/ climbed up along the sidewall of the spacer. As a result, both NMOSFETs and PMOSFETs with 45-nm thick Ti film did not operate in the electrically open mode. This indicates that the conditions of the full silicidation for ultrathin SIMOX MOSFETs has to be carefully determined from the view point of Ti and Si composition.<<ETX>>

Three dimensional topography simulation model using diffusion equation

An etching model for three-dimensional topography simulation is proposed in which the topography is deduced by solving the diffusion equation. A 3-D topography simulator called 3-D MULSS (multilayer shape simulator) has been developed on the basis of this model. Using this program, contact hole and trench etching was simulated exactly, and the computation was extremely fast.<<ETX>>

Laboratory and factory automation for VLSI development and mass production

The authors present a concept for automation in VLSI fabrication and examples of both the automated laboratory line and the mass production line. Particular attention is given to the aims of and items for automation, the system design for laboratory automation, the CAPS (computer-aided processing system) design, the computer hierarchy of the factory line, and the data acquisition and analysis system.<<ETX>>

Consideration of the structure design for thin SOI/MOSFET under and beyond the half micron regime

A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operation due to a floating body structure. Latch-up phenomena in a unit NMOS diminishes the reliable operation of the CMOS circuit. The problem can be solved by lowering the drain electric field to reduce generated holes from impact ionization which reinforces parasitic bipolar operation. The authors studied the LDD (lightly doped drain) structure and an advanced gate overlapped LDD structure for device application of the thin-SOI/MOSFET under and beyond the half-micron regime.<<ETX>>

Deep submicron device with buried insulator between source/drain polysilicon (BIPS)

A novel isolation technology, called buried insulator between source/drain polysilicon (BIPS), is described. The BIPS isolation structure consists of refilling CVD (chemical vapor deposition) oxides in openings between source/drain polysilicon patterns by double photoresist etchback. A defect- and birds beak-free process can be realized by this isolation. Devices with BIPS isolation are compared with LOCOS (local oxidation of silicon) with respect to isolation parasitic effects and current drive capability. A 0.5- mu m isolation is achieved, and the narrow channel effects are almost suppressed with BIPS isolation. The subthreshold characteristics of devices with BIPS isolation give the same shape value as those for conventional devices with LOCOS isolation. A ring oscillator with BIPS isolation exhibits a propagation delay time of 69 ps/gate.<<ETX>>