Katsuhiro Tsukamoto

A complete substrate current model including band-to-band tunneling current for circuit simulation

A simple and accurate substrate current model that is valid in the whole operation region of a MOSFET with various dimensions is presented. The theory is based on hot-carrier induced impact ionization and band-to-band tunneling (BTBT). All the parameters in the model can be assigned proper physical meanings and are easily extracted from the measurement data. The model is incorporated in a Mitsubishi Circuit Simulator (MICS). Both the accuracy and the efficiency of the model are shown by experiment and simulation, and hence make the simulator useful for designers who care about low power applications. >

Self-gettering and proximity gettering for buried layer formation by MeV ion implantation

The authors studied the characteristics of the junction leakage current of diodes having a buried layer formed by high-energy boron, phosphorus, and arsenic implantation. A remarkable decrease in junction leakage current to the level comparable to that without a buried layer was observed with doses of over 3*10/sup 14/ ions/cm/sup 2/ (self-gettering). The effects of additional high-energy carbon, oxygen, and fluorine implantation on the buried layer were also investigated. A strong gettering effect in reducing the leakage current of the diode was found (proximity gettering). The gettering by secondary defects induced by high-energy ion implantation is found to be a major cause of these phenomena.<<ETX>>

Practical attenuated phase-shifting mask with a single-layer absorptive shifter of MoSiO and MoSiON for ULSI fabrication

Attenuated phase-shifting mask with a single-layer absorptive shifter with MoSiO or MoSiON films has been developed. These films satisfies the condition both the 180-degree phase shift and the transmittance between 5 and 20%. Conventional mask processes, such as etching, cleaning, defect inspection and defect repair, can be used for the fabrication. Defect-free masks for hole layers of 64 M-bit DRAM have been obtained. Using this mask, the focus depth of 0.35-/spl mu/m hole is improved from 0.6 /spl mu/m to 1.5 /spl mu/m.<<ETX>>

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<<ETX>>

A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<<ETX>>

Effect of duty ratio of line and space in phase-shifting lithography

This paper discusses the effect of duty ratio of line and space patterns and the coherency of illumination for the projection system on the lithographic characteristics, which must be taken into consideration in designing LSI patterns with an alternated type phase-shifting method. It was found that the alternated phase-shifting method improved the DOF for space patterns using a width smaller than the line width. On the contrary, there was no effect for narrow line patterns when the space width was larger than twice the line width. It was also found that the DOF became larger, when the coherency became higher using both the alternated and the conventional mask for line patterns having a width smaller than the space width. It is concluded that a high coherency must be chosen for the phase-shifting method.

Deep submicron device with buried insulator between source/drain polysilicon (BIPS)

A novel isolation technology, called buried insulator between source/drain polysilicon (BIPS), is described. The BIPS isolation structure consists of refilling CVD (chemical vapor deposition) oxides in openings between source/drain polysilicon patterns by double photoresist etchback. A defect- and birds beak-free process can be realized by this isolation. Devices with BIPS isolation are compared with LOCOS (local oxidation of silicon) with respect to isolation parasitic effects and current drive capability. A 0.5- mu m isolation is achieved, and the narrow channel effects are almost suppressed with BIPS isolation. The subthreshold characteristics of devices with BIPS isolation give the same shape value as those for conventional devices with LOCOS isolation. A ring oscillator with BIPS isolation exhibits a propagation delay time of 69 ps/gate.<<ETX>>