Yasuhiro Fujimura

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

High-speed, high-density 4-4.5Mb CMOS cache SRAMs do not have speed comparable to that of a 4.5Mb BiCMOS SRAM. This 4.5Mb CMOS SRAM has access time equivalent to that of a BiCMOS SRAM. Key techniques for achieving this speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.

A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster

The key to improving the performance of a single chip processor is to incorporate many varieties of SRAM macros with a word/bit-flexible configuration. To improve the performance even more, a configurable organization technique featuring a leaf cell design is proposed. In applying the technique, the timing design became too critical for the high-performance processor. An automatic timing adjuster is thus proposed to adjust the sense amplifier activation timing automatically in each organization. In addition, a low Vth MOS transistor is applied in order to improve access time. To overcome the increase in current leakage due to a low Vth, a back-bias control circuit is also proposed. These techniques in conjunction with a 0.25 /spl mu/m CMOS process make it possible to achieve a 0.9 ns access, 700 MHz SRAM macro.

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions

A 1.5-ns-access 500-MHz synonym hit RAM has been developed using 0.25-/spl mu/m CMOS technology, which is the macro-cell to be used in microprocessor chips. We have proposed a virtual cache system with a synonym hit RAM, which achieves both high speed and large capacity because it solves the synonym problem that occurs with large-capacity cache systems. In this system, the RAM macro needs 576-bit parallel comparison and parity check functions. The configuration used achieves testability and low-power dissipation of large 576-bit data output. Moreover, the dynamic-NOR with a dynamic-inverter and sense-amplifier activation pulse generator are essential for reducing the comparison delay.