Akihisa Uchida

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8- mu m SICOS technology. High-load and low-load resistors in this new memory cell are formed by using double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 mu m/sup 2/) and a reasonable chip size (85.8 mm/sup 2/). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAMs. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity. >

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<<ETX>>

An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM

An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<<ETX>>

High capacitance ultra-thin Ta 2 O 5 dielectric film applied to a high-speed bipolar memory cell

A new capacitor technology, with extremely thin Ta<inf>2</inf>O<inf>5</inf>film deposition and weakspot oxidation, is developed to realize high capacitance and high reliability. The Ta<inf>2</inf>O<inf>5</inf>film was reactively sputtered and followed by the weakspot oxidation. The oxidation improves the breakdown voltage by selectively oxidizing Si surface at weakspots where Ta<inf>2</inf>O<inf>5</inf>is locally thin. Consequently it reduces the defect density of the Ta<inf>2</inf>O<inf>5</inf>capacitor with least reduction of capacitance. This technology is based on a newly discovered fact that Ta<inf>2</inf>O<inf>5</inf>film below 200 Å remains in amorphous state with high dielectric breakdown strength even after heat treatments up to 1000 °C. Application of the Ta<inf>2</inf>O<inf>5</inf>capacitor to a switched-load resistor memory makes it possible to reduce the memory cell area to one third that of a conventional one. The memory provides high speed operation, and has sufficient soft error immunity.

A 3.5ns, 2W, 20mm 2 16Kb ECL bipolar RAM

THIS PAPER WILL DESCRIBE a 3.5ns ECL 16Kb bipolar RAM with a power dissipation of 2W, cell size of 4 9 5 ~ 2 and chip size of 20mm2. The most critical requirements for bipolar RAMs are high speed, low power dissipation and small chip size. Two circuit techniques are proposed to meet the foregoing criteria: ( I ) a Schottky barrier diode (SBD) decoder combined with an address buffer and a latch circuit having three-level VBB; ( 2 ) a Darlington word driver having double-stage discharge circuits. The SBD decoder circuit combined with the address buffer and latch circuits is shown in Figure 1. The decoder reduces access time by 20% compared to a conventional multi-emitter decoder, because the parasitic capacitance CDE at the decoder output can be reduced by about 65%. The lower capacitance is due to the small area and small junction capacitance per unit area. Two SBDs have been connected in series to obtain a forward voltage higher than a base-emitter voltage VBE of the transistor QE. This enables the decoder to be completely cut off, insuring a sufficiently high level at the decoder output. To realize even higher speeds at the system level, an on-chip buffer and latch must be combined with the SBD decoder. However, a simple combination of the conventional address buffer and latch using a series gate’ and SBD decoder cannot be used because of transistor (Ql /Q2) saturation under a given supply voltage (-5.2V); Figure 1. To overcome this problem, an address buffer and latch with a threelevel VBB, also shown in Figure 1, is proposed. The latch operation can be performed by the three-level VBB without any loss in speed. Until the clock CLK turns on, the VBB generator offers a VBB in accordance with the previous address input (ADR) levels as shown in Figure 2. That is, the VBB is set to a lower (higher) level than any address input level for high (low) level address input. Therefore, the outputs of the address buffer are held high or low regardless of the following address input changes. When the clock CLK turns on at to, the output of the VBB generator is switched to a standard VBB level for a 10K or lOOK logic family. Thus, the outputs of the address buffers can be changed in accordance with the address inputs. This address information is retained when the CLK turns off again. Figure 3 shows a Darlington word driver using double-stage discharge circuits connected to each of the transistor emitters. Sufficient discharge currents are provided (I1 = 2mA, I2 = 6mA) without a significant voltage drop on the word line. Conventional delayed discharge circuits are also used at the end of the word lines to increase the cell margin. Since both discharge circuits are delay-type, it is possible to maintain a high current after the word line voltage switches to a low level. The driver reduces further the access time by about 15Yc. The increase in power dissipation is negligibly small in spite of the high

Technology improvement for high speed ECL RAMs

The trends in high speed ECL random access memories (RAMs) are reviewed with emphasis on memory cell improvements for achieving high speed performance. State-of-the-art technologies including bipolar, BICMOS, memory-with-logic modules and logic-in-memory LSIs are discussed. Finally, some prospects for ultra-high speed RAMs are proposed.