Yen-Ya Hsu

Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

A 30×30 nm2 HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (RHIGH) and low resistance (RLOW) are proposed for the array to ensure a good operation window. A thin AlOx buffer layer under the HfOx layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.

Evidence and solution of over-RESET problem for HfO X based resistive memory with sub-ns switching speed and high endurance

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

Robust High-Resistance State and Improved Endurance of

The effect of operation current on the high-resistance state and the endurance for the HfOx-based resistive device is comprehensively studied. Due to the current overshoot by the parasitic capacitances, an excess current leakage for the high resistance state of the 1R device after the forming and SET stages is observed. The accelerated degradation of the high-resistance state for the HfOx device undergoing a high-operation-current stage is revealed for the first time. As the compliance current increases beyond 500 μA, the resistance of the high-resistance state of the device deceases drastically. A possible scenario about the correlation between the high-resistance state and the compliance current based on the filament model is proposed. By suppressing the current overshoot with the 1T1R device, the high-resistance state (>; 1 MΩ) and excellent endurance (>; 108 cycles) for the HfOx resistive memory are demonstrated.

\hbox{HfO}_{X}

Resistive random access memory (RRAM or ReRAM) is a non-volatile memory (NVM) technology that consumes minimal energy while offering sub-nanosecond switching. In addition, the data stability against high temperature and cycling wear is very robust, allowing new NVM applications in a variety of markets (automotive, embedded, storage, RAM). Based on sudden conduction through oxide insulators, the characteristics of RRAM technology have still yet to be fully described. In this paper, we present our current understanding of this very promising technology.

Resistive Memory by Suppression of Current Overshoot

In this paper, statistical measurements on the retention behavior of the stable HfOBx-based RRAM under various thermal/voltage/cycling stresses are investigated. Testing results show that, data retention of high resistance state (HRS) of a RRAM is insensitive to temperature and cycling-aging. An empirical equation involving the voltage/thermal/cycling-stress acceleration is given for lifetime prediction. 10 years lifetime can be obtained with a constant read voltage of 0.2 V even at 160 °C. Also the set time of the RRAM extrapolated by the empirical equation coincides with the experiment value. In addition, the shallow Weibull slope of the retention time can be improved when the variations of the initial resistance is well controlled.

Resistance switching for RRAM applications

Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM) [1,2], reliability issue is still the most concern, but less addressed [3,4]. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically shrink the reliability margin for reading process [4]. Inserting a thin Al2O3 between the transition metal oxide and bottom electrode was proposed previously to improve read disturb immunity at room temperature [4]. However, the effect of high temperature (125°C) on the read disturb of this stacked layer (HfOx/Al2O3) has not yet been studied.

Statistical analysis of retention behavior and lifetime prediction of HfOBxB-based RRAM

Because of the benefits of low power and high speed, binary oxide based resistive memory (RRAM) is considered the potential candidate of the next generation nonvolatile memory [1,2]. To be implemented in the future technology node, the scalability of memory device down to nanoscale is an important criterion for RRAM technology development. Through the integration with concave structure, it has been demonstrated that, even in nanoscale, the HfO2 based resistive memory with a Ti reactive layer still exhibited bipolar resistance switch (RS) characteristics [3]. However, the large parasitic capacitance from the parallel capacitor consisting of TiN/Ti/HfO2/SiO2/TiN in the concave structure degrades the memory performance [3]. Besides, the complexity of process for the concave structure, which needs an additional process to fabricate a SiO2 supporting layer, makes it less attractive to IC industry.

Comprehensively study of read disturb immunity and optimal read scheme for high speed HfOx based RRAM with a Ti layer

Recently, binary oxide based resistive memory exhibits a large sensing margin, low power, and high speed as a promising candidate for the next generation nonvolatile memory [1,2]. The compliance current (IC) is required for the device under forming/SET step to prevent the permanent damage. The extraordinarily high current overshoot, attributed to the effect of parasitic capacitance during the forming/SET operation, is addressed [3,4]. The correlation between the IC and maximum RESET current (IRESET, max) is also disclosed [5]. However, the influence of IC and the current overshoot on the resistance of high resistance state (RHIGH) and the stability during endurance are less addressed. In addition, the impact of the thickness of insulator on the current overshoot with an identical Ic for the bipolar resistive device has not yet been studied.

Scalability with silicon nitride encapsulation layer for Ti/HfOx pillar RRAM

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

Impact of compliance current overshoot on high resistance state, memory performance, and device yield of HfO x based resistive memory and its solution

HfOx RRAM is a most promising candidate for next generation nonvolatile memory [1,2] with highest endurance, speed till now but bipolar switching affects the selection of steering device, performance and applications. Bipolar and unipolar RRAMs have their advocators [1,3]. Cell area of 4F2 and/or 3D stacking for high density applications is the determining factor of preferring unipolar device. High operation power, low endurance and slow speed are most crucial issues. Recently, polarity of RRAM reported to be a strong function of top (anodic) electrode (TE) material [4,5]. In this work, HfOx-based RRAM is studied by selection of TE stacking structures to find unipolar HfOx-based RRAM device structures with better performance.