Yohei Yagishita

A 76–81 GHz high efficiency power amplifier for phased array automotive radar applications

This paper describes the implementation of 76-81 GHz power amplifier (PA) in 65 nm CMOS technology. A customized transistor model enables the designing circuits operating at mm-wave band. The output matching of the PA was composed of low-pass network to reduce both footprint and matching loss. This makes the PA ideal for phased array radars. The measured results at 79 GHz achieved the small signal gain of 25.1 dB, the saturated output power (Psat) of 11.5 dBm, and the power added efficiency (PAE) of 13.6% at the supply voltage of 0.8 V. These results agreed with the simulation.

265-GHz, 10-dB gain amplifier in 65-nm CMOS using on-wafer TRL calibration

In this paper, a 65-nm CMOS amplifier MMIC operating around 265 GHz is presented. To obtain a small signal gain of the amplifier in a frequency region close to Fmax (Maximum oscillation frequency) of a transistor, a neutralization technique of a feedback capacitance as well as a transistor model to neutralize it precisely are needed. For this purpose, the key is a de-embedding technique. To extract the intrinsic transistor characteristics from a test pattern for measurement, we employ an on-wafer TRL (Through-Reflect-Line) calibration method. In this method, the calibration patterns including Through, Reflect, and Line are fabricated on the same wafer with the transistor for modeling. With the help of the precise model based on on-wafer TRL, we can successfully obtain a gain of 10dB around 265 GHz, and an excellent agreement with simulation and measurement results.