Younsung Choi

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

Improved silicide formation by improved sige faceting

Dummy gate placement methodology to enhance integrated circuit performance

OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LINER TECHNOLOGY

EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS

DUAL POCKET APPROACH IN PFETS WITH EMBEDDED SI-GE SOURCE/DRAIN

METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH ANGLE SOURCE/DRAIN IMPLANTS

LASER ANNEALS FOR REDUCED DIODE LEAKAGE

FORMING SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET