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Featured researches published by Yue Liang.


MRS Proceedings | 2009

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

Dechao Guo; Kathryn T. Schonenberg; Jie Chen; Daniel J. Jaeger; Pranita Kulkarni; Unoh Kwon; Yue Liang; Joyce C. Liu; Liyang Song; F. Arnaud; Huiming Bu; Michael P. Chudzik; William K. Henson; Philip J. Oldiges; M. Sherony; A. Steegen; Voon-Yew Thean; M. Khare

For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.


Archive | 2011

Dual metal and dual dielectric integration for metal high-K FETs

Michael P. Chudzik; William K. Henson; Rashmi Jha; Yue Liang; Richard S. Wise


Archive | 2010

Method and structure for gate height scaling with high-k/metal gate technology

Michael P. Chudzik; Ricardo A. Donaton; William K. Henson; Yue Liang


Archive | 2010

Semiconductor device having dual metal gates and method of manufacture

Unoh Kwon; Siddarth A. Krishnan; Takashi Ando; Michael P. Chudzik; Martin M. Frank; William K. Henson; Rashmi Jha; Yue Liang; Vijay Narayanan; Keith Kwong Hon Wong


Archive | 2010

Threshold Voltage Adjustment Through Gate Dielectric Stack Modification

Brian J. Greene; Michael P. Chudzik; Shu-Jen Han; William K. Henson; Yue Liang; Edward P. Maciejewski; Myung-Hee Na; Edward J. Nowak; Xiaojun Yu


Archive | 2015

Tucked active region without dummy poly for performance boost and variation reduction

Brian J. Greene; Yue Liang; Xiaojun Yu


Archive | 2013

METHOD AND STRUCTURE FOR pFET JUNCTION PROFILE WITH SiGe CHANNEL

Kern Rim; William K. Henson; Yue Liang; X. Wang


Archive | 2013

DUMMY GATE INTERCONNECT FOR SEMICONDUCTOR DEVICE

Brian J. Greene; Yue Liang; Xiaojun Yu


Archive | 2012

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

Dureseti Chidambarrao; Sunfei Fang; Yue Liang; Xiaojun Yu; Jun Yuan


Archive | 2011

Threshold voltage adjustment for thin body MOSFETs

Mary Jane Brodsky; Ming Cai; Dechao Guo; William K. Henson; Shreesh Narasimha; Yue Liang; Liyang Song; Yanfeng Wang; Chun-Chen Yeh

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