Hisao Asakura

Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory

The threshold voltage offsets of paired p+-gate p-channel metal-oxide-semiconductor field effect transistors in high-density dynamic random access memory is investigated. The threshold voltage offset is shown to be mainly due to segregation of phosphorus at the edges of the shallow trench isolation when the gate oxide is formed. A 20-mV threshold-voltage offset was experimentally eliminated through control of the phosphorus concentration and the layout of the cross-couplings of sense amplifiers. It is expected that reduction in the threshold voltage offset will improve the retention times of gigabit-scale dynamic random access memory.