Yuichiro Sasaki

Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors

Low frequency noise and hot carrier reliability analysis of the plasma doping scheme are investigated for advanced fin field effect transistor (FinFET) conformal doping. Plasma doping improves device performances and hot carrier reliability for both fin resistors and FinFETs due to the absence of crystalline damage for narrow fins. One decade lower noise level and Coulomb scattering coefficient related to the crystalline damage suppression are observed for the plasma doping compared to the standard ion-implantation.

Improved sidewall doping of extensions by AsH 3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs

We demonstrate a novel photoresist-compatible FinFET doping technique that combines the advantages of deposition and implantation. Energy and deposition thickness optimization for the Ion Assisted Deposition and Doping (IADD) process provides excellent doping of nMOS extensions, thus reducing external resistance REXT. On current ION is improved by 6-8% for LG of 26-30 nm and by 15% for LG of 20 nm, with better SCE and DIBL.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm^-3) was used as a diffusion source. SiO₂ cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO₂ exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO₂ cap stack after drive-in anneal, the PSG/SiO₂ cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current I_ON is improved by 20% for L_G in the 30-24 nm range, with similar I_OFF and better DIBL compared to P ion implanted reference.

First demonstration of 15nm-W FIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G_M,SAT,EXT / SS_SAT of 250 μS.μm^-1 / 130 mV.dec^-1 (at the targeted V_DS=0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

High performance n-MOS finFET by damage-free, conformal extension doping

A solution for conformal n-type finFET extension doping is demonstrated, yielding ION values of 1.23 mA/µm at IOFF=100 nA/um at 1V. This high device performance results from 40% reduced external resistance, which in term is stemming from 130% increased fin sidewall doping (confirmed by SIMS, SSRM and Atom Probe) relative to ion implant process. In this work we also report lowered gate leakage due to the damage-free extension doping.

A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.

A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved ION, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (LG) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.

Atom Probe Tomography for 3D-dopant analysis in FinFET devices

As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate methodology this is feasible using Atom Probe Tomography (APT). We extract the 3D-dopant profile and important parameters such as gate overlap and profile steepness, from transistor formed with plasma doping processes. Analyzing samples with different doping processes, the APT results are entirely consistent with device performances (Ioff vs. Ion).

Junction strategies for 1x nm technology node with FINFET and high mobility channel

Junction strategies for FINFETs and high mobility channel devices in 1× nm node are discussed. Doping conformality and doping damage control are the keys for high performance scaled FINFETs. Damage-less conformal fin doping can be provided by Self Regulatory Plasma Doping (SRPD) process, based on radical absorption in low energy plasma and subsequent drive-in anneal. SRPD demonstrates 20% Ion gain as compared to an ion implantation reference. The Implant Free Quantum Well (IFQW) device, featuring high mobility QW channel and doped epi raised Source/Drain (rSD), is one of the most promising device architectures for high mobility channel devices. Carrier confinement in QW channel enables good short channel control without halo, which in turn leads to reduced variability. Doped epi rSD enables low temperature junction anneal that maintains high channel mobility. SiGe IFQW device with eSiGe epi SD shows very high Ion of 1.28mA/μm at Ioff = 160nA/μm at gate length/width of 30nm/0.16μm.

Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies

This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.